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PIC12F510/16F506 Data Sheet
8/14-Pin, 8-Bit Flash Microcontroller
*8-bit, 8-pin Devices Protected by Microchip's Low Pin Count Patent: U.S. Patent No. 5,847,450. Additional U.S. and foreign patents and applications may be issued or pending.
(c) 2006 Microchip Technology Inc.
Preliminary
DS41268B
Note the following details of the code protection feature on Microchip devices: * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable."
*
* *
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.
Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active Thermistor, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, Real ICE, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and Zena are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2006, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper.
Microchip received ISO/TS-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October 2003. The Company's quality system processes and procedures are for its PICmicro(R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified.
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(c) 2006 Microchip Technology Inc.
PIC12F510/16F506
8/14-Pin, 8-Bit Flash Microcontroller
Devices Included In This Data Sheet:
* PIC16F506 * PIC12F510 * Selectable oscillator options: - INTOSC: 4/8 MHz precision Internal oscillator - EXTRC: External low-cost RC oscillator - XT: Standard crystal/resonator - LP: Power-saving, low-frequency crystal - HS: High-speed crystal/resonator (PIC16F506 only) - EC: High-speed external clock input (PIC16F506 only) * Analog-to-Digital (A/D) Converter: - 8-bit resolution - 4-input channels (1 channel is dedicated to conversion of the internal 0.6V absolute voltage reference) * High current sink/source for direct LED drive * 8-bit real-time clock/counter (TMR0) with 8-bit programmable prescaler
High-Performance RISC CPU:
* Only 33 single-word instructions to learn * All single-cycle instructions except for program branches, which are two-cycle * 12-bit wide instructions * 2-level deep hardware stack * Direct, Indirect and Relative Addressing modes for data and instructions * 8-bit wide data path * 10 Special Function Hardware registers (PIC12F510) * 13 Special Function Hardware registers (PIC16F506) * Operating speed: - DC - 8 MHz Crystal Oscillator (PIC12F510) - DC - 500 ns instruction cycle (PIC12F510) - DC - 20 MHz Crystal Oscillator (PIC16F506) - DC - 200 ns instruction cycle (PIC16F506)
Low-Power Features/CMOS Technology:
* Operating Current: - < 170 A @ 2V, 4 MHz * Standby Current: - 100 nA @ 2V, typical * Low-power, high-speed Flash technology: - 100,000 cycle Flash endurance - > 40-year retention * Fully static design * Wide operating voltage range: 2.0V to 5.5V * Wide temperature range: - Industrial: -40C to +85C - Extended: -40C to +125C
Special Microcontroller Features:
* 4 or 8 MHz selectable precision internal oscillator: - Factory calibrated to 1% * In-Circuit Serial ProgrammingTM (ICSPTM) * In-Circuit Debugging (ICD) support * Power-on Reset (POR) * Device Reset Timer (DRT): - Short DRT (1.125 ms, typical) for INTOSC, EXTRC and EC - DRT (18 ms, typical) for HS, XT and LP * Watchdog Timer (WDT) with dedicated on-chip RC oscillator for reliable operation * Programmable code protection * Multiplexed MCLR input pin * Selectable internal weak pull-ups on I/O pins * Power-Saving Sleep mode * Wake-up from Sleep on pin change * Wake-up from Sleep on comparator change
Peripheral Features (PIC12F510):
* 6 I/O pins: - 5 I/O pins with individual direction control - 1 input only pin * 1 Analog Comparator with absolute reference
Peripheral Features (PIC16F506):
* 12 I/O pins: - 11 I/O pins with individual direction control - 1 input only pin * 2 Analog Comparators with absolute reference and programmable reference
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PIC12F510/16F506
Program Memory Device Flash (words) PIC16F506 PIC12F510 1024 1024 SRAM (bytes) 67 38 12 6 Data Memory I/O Timers 8-bit 1 1
Pin Diagrams
PDIP, SOIC and TSSOP
VDD RB5/OSC1/CLKIN RB4/OSC2/CLKOUT RB3/MCLR/VPP RC5/T0CKI RC4/C2OUT RC3 1 14 13 VSS RB0/AN0/C1IN+/ICSPDAT RB1/AN1/C1IN-/ICSPCLK RB2/AN2/C1OUT RC0/C2IN+ RC1/C2INRC2/CVREF
3 4 5 6 7
PIC16F506
2
12 11 10 9 8
PDIP, SOIC, MSOP
VDD GP5/OSC1/CLKIN GP4/OSC2 GP3/MCLR/VPP 1 2 3 4 8 7 6 5 VSS GP0/AN0/C1IN+/ICSPDAT GP1/AN1/C1IN-/ICSPCLK GP2/AN2/T0CKI/C1OUT
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PIC12F510
(c) 2006 Microchip Technology Inc.
PIC12F510/16F506
Table of Contents
1.0 General Description...................................................................................................................................................................... 5 2.0 PIC12F510/16F506 Device Varieties .......................................................................................................................................... 7 3.0 Architectural Overview ................................................................................................................................................................. 9 4.0 Memory Organization ................................................................................................................................................................. 15 5.0 I/O Port ....................................................................................................................................................................................... 27 6.0 TMR0 Module and TMR0 Register............................................................................................................................................. 39 7.0 Comparator(s) ............................................................................................................................................................................ 43 8.0 Comparator Voltage Reference Module (PIC16F506 only)........................................................................................................ 49 9.0 Analog-to-Digital (A/D) Converter............................................................................................................................................... 51 10.0 Special Features Of The CPU.................................................................................................................................................... 55 11.0 Instruction Set Summary ............................................................................................................................................................ 71 12.0 Development Support................................................................................................................................................................. 79 13.0 Electrical Characteristics ............................................................................................................................................................ 83 14.0 DC and AC Characteristics Graphs and Charts ......................................................................................................................... 96 15.0 Packaging................................................................................................................................................................................... 98 Index .................................................................................................................................................................................................. 107 The Microchip Web Site ..................................................................................................................................................................... 109 Customer Change Notification Service .............................................................................................................................................. 109 Customer Support .............................................................................................................................................................................. 109 Reader Response .............................................................................................................................................................................. 110 Product Identification System ............................................................................................................................................................ 111
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Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: * Microchip's Worldwide Web site; http://www.microchip.com * Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using.
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(c) 2006 Microchip Technology Inc.
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PIC12F510/16F506
1.0 GENERAL DESCRIPTION
1.1 Applications
The PIC12F510/16F506 devices from Microchip Technology are low-cost, high-performance, 8-bit, fullystatic, Flash-based CMOS microcontrollers. They employ a RISC architecture with only 33 single-word/ single-cycle instructions. All instructions are singlecycle except for program branches, which take two cycles. The PIC12F510/16F506 devices deliver performance in an order of magnitude higher than their competitors in the same price category. The 12-bit wide instructions are highly symmetrical, resulting in a typical 2:1 code compression over other 8-bit microcontrollers in its class. The easy-to-use and easyto-remember instruction set reduces development time significantly. The PIC12F510/16F506 products are equipped with special features that reduce system cost and power requirements. The Power-on Reset (POR) and Device Reset Timer (DRT) eliminate the need for external Reset circuitry. There are four oscillator configurations to choose from (six on the PIC16F506), including INTOSC Internal Oscillator mode and the power-saving LP (Low-power) Oscillator mode. Power-saving Sleep mode, Watchdog Timer and code protection features improve system cost, power and reliability. The PIC12F510/16F506 devices allow the customer to take full advantage of Microchip's price leadership in Flash programmable microcontrollers, while benefiting from the Flash programmable flexibility. The PIC12F510/16F506 products are supported by a full-featured macro assembler, a software simulator, an in-circuit emulator, a `C' compiler, a low-cost development programmer and a full featured programmer. All the tools are supported on IBM(R) PC and compatible machines. The PIC12F510/16F506 devices fit in applications ranging from personal care appliances and security systems to low-power remote transmitters/receivers. The Flash technology makes customizing application programs (transmitter codes, appliance settings, receiver frequencies, etc.) extremely fast and convenient. The small footprint packages, for through hole or surface mounting, make these microcontrollers perfect for applications with space limitations. Low-cost, lowpower, high-performance, ease-of-use and I/O flexibility make the PIC12F510/16F506 devices very versatile, even in areas where no microcontroller use has been considered before (e.g., timer functions, logic and PLDs in larger systems and coprocessor applications).
TABLE 1-1:
Clock Memory Peripherals Features
PIC12F510/16F506 DEVICES
PIC16F506 Maximum Frequency of Operation (MHz) Flash Program Memory Data Memory (bytes) Timer Module(s) Wake-up from Sleep on Pin Change I/O Pins Input Only Pin Internal Pull-ups In-Circuit Serial Programming Number of Instructions Packages 20 1024 67 TMR0 Yes 11 1 Yes Yes 33 14-pin PDIP, SOIC, TSSOP PIC12F510 8 1024 38 TMR0 Yes 5 1 Yes Yes 33 8-pin PDIP, SOIC, MSOP
The PIC12F510/16F506 devices have Power-on Reset, selectable Watchdog Timer, selectable code-protect, high I/O current capability and precision internal oscillator. The PIC12F510/16F506 device uses serial programming with data pin RB0/GP0 and clock pin RB1/GP1.
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PIC12F510/16F506
2.0 PIC12F510/16F506 DEVICE VARIETIES
2.2 Serialized Quick Turn ProgrammingSM (SQTPSM) Devices
A variety of packaging options are available. Depending on application and production requirements, the proper device option can be selected using the information in this section. When placing orders, please use the PIC12F510/16F506 Product Identification System at the back of this data sheet to specify the correct part number.
Microchip offers a unique programming service, where a few user-defined locations in each device are programmed with different serial numbers. The serial numbers may be random, pseudo-random or sequential. Serial programming allows each device to have a unique number, which can serve as an entry code, password or ID number.
2.1
Quick Turn Programming (QTP) Devices
Microchip offers a QTP programming service for factory production orders. This service is made available for users who choose not to program medium-to-high quantity units and whose code patterns have stabilized. The devices are identical to the Flash devices, but with all Flash locations and fuse options already programmed by the factory. Certain code and prototype verification procedures do apply before production shipments are available. Please contact your local Microchip Technology sales office for more details.
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PIC12F510/16F506
3.0 ARCHITECTURAL OVERVIEW
The high performance of the PIC12F510/16F506 devices can be attributed to a number of architectural features commonly found in RISC microprocessors. The PIC12F510/16F506 devices use a Harvard architecture in which program and data are accessed on separate buses. This improves bandwidth over traditional von Neumann architectures where program and data are fetched on the same bus. Separating program and data memory further allows instructions to be sized differently than the 8-bit wide data word. Instruction opcodes are 12 bits wide, making it possible to have all single-word instructions. A 12-bit wide program memory access bus fetches a 12-bit instruction in a single cycle. A two-stage pipeline overlaps fetch and execution of instructions. Consequently, all instructions (33) execute in a single cycle (200 ns @ 20 MHz, 1 s @ 4 MHz) except for program branches. Table 3-1 lists program memory (Flash) and data memory (RAM) for the PIC12F510/16F506 devices. The ALU is 8 bits wide and capable of addition, subtraction, shift and logical operations. Unless otherwise mentioned, arithmetic operations are two's complement in nature. In two-operand instructions, one operand is typically the W (working) register. The other operand is either a file register or an immediate constant. In single-operand instructions, the operand is either the W register or a file register. The W register is an 8-bit working register used for ALU operations. It is not an addressable register. Depending on the instruction executed, the ALU may affect the values of the Carry (C), Digit Carry (DC) and Zero (Z) bits in the STATUS register. The C and DC bits operate as a borrow and digit borrow out bit, respectively, in subtraction. See the SUBWF and ADDWF instructions for examples. A simplified block diagram is shown in Figure 3-1 for PIC12F510 with the corresponding device pins described in Table 3-2. A simplified block diagram for PIC16F506 is shown in Figure 3-2 with the corresponding device pins described in Table 3-3.
TABLE 3-1:
Device
PIC12F510/16F506 MEMORY
Memory Program Data 38 x 8 67 x 8
PIC12F510 PIC16F506
1024 x 12 1024 x 12
The PIC12F510/16F506 devices can directly or indirectly address its register files and data memory. All Special Function Registers (SFR), including the PC, are mapped in the data memory. The PIC12F510/ 16F506 devices have a highly orthogonal (symmetrical) instruction set that makes it possible to carry out any operation, on any register, using any addressing mode. This symmetrical nature and lack of "special optimal situations" make programming with the PIC12F510/16F506 devices simple, yet efficient. In addition, the learning curve is reduced significantly. The PIC12F510/16F506 devices contain an 8-bit ALU and working register. The ALU is a general purpose arithmetic unit. It performs arithmetic and Boolean functions between data in the working register and any register file.
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PIC12F510/16F506
FIGURE 3-1: PIC12F510 SERIES BLOCK DIAGRAM
10-11 Flash Program Counter 8 GPIO GP0/ICSPDAT GP1/ICSPCLK GP2 GP3 GP4 GP5
Data Bus
1K x 12
Program Memory Program Bus 12 Instruction Reg Direct Addr 5 STACK 1 STACK 2 RAM
38 bytes
File Registers RAM Addr 9
Addr MUX 5-7 Indirect Addr
FSR Reg STATUS Reg 8 3 Device Reset Timer Instruction Decode & Control Timing Generation Power-on Reset Watchdog Timer Internal RC Clock 8 W Reg VREF ALU
MUX C1IN+ C1INC1OUT
Comparator
OSC1/CLKIN OSC2
Timer0 MCLR VDD, VSS
8-bit ADC
AN0 AN1 AN2
T0CKI
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TABLE 3-2:
Name GP0/AN0/C1IN+/ICSPDAT
PIN DESCRIPTIONS - PIC12F510
I/O/P Type GP0 Input Type TTL Output Type CMOS Description Bidirectional I/O port. Can be software programmed for internal weak pull-up and wake-up from Sleep on pin change. ADC channel input. Comparator input. In-Circuit Serial Programming data pin. Bidirectional I/O port. Can be software programmed for internal weak pull-up and wake-up from Sleep on pin change. ADC channel input. Comparator input. In-Circuit Serial Programming clock pin. Bidirectional I/O port. ADC channel input. Timer0 clock input. Comparator output. Standard TTL input. Can be software programmed for internal weak pull-up and wake-up from Sleep on pin change. MCLR input - weak pull-up always enabled in this mode. Programming Voltage input. Bidirectional I/O port. XTAL oscillator output pin. Bidirectional I/O port. XTAL oscillator input pin. EXTRC Schmitt Trigger input. Positive supply for logic and I/O pins. Ground reference for logic and I/O pins.
AN0 C1IN+ ICSPDAT GP1/AN1/C1IN-/ICSPCLK GP1
AN AN ST TTL
-- -- CMOS CMOS
AN1 C1INICSPCLK GP2/AN2/T0CKI/C1OUT GP2 AN2 T0CKI C1OUT GP3/MCLR/VPP GP3
AN AN ST TTL AN ST -- TTL
-- -- -- CMOS -- -- CMOS --
MCLR VPP GP4/OSC2 GP5/OSC1/CLKIN GP4 OSC2 GP5 OSC1 CLKIN VDD VSS VDD VSS
ST High Voltage TTL -- TTL XTAL ST P P
-- -- CMOS XTAL CMOS -- -- -- --
Legend: I = input, O = output, I/O = input/output, P = power, -- = Not Used, TTL = TTL input, ST = Schmitt Trigger input, AN = Analog Voltage
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PIC12F510/16F506
FIGURE 3-2: PIC16F506 SERIES BLOCK DIAGRAM
10 Program Counter Flash 1K x 12 Program Memory 8
Data Bus
PORTB RB0/ICSPDAT RB1/ICSPCLK RB2 RB3 RB4 RB5 PORTC
STACK 1 STACK 2
Program Bus
RAM 67 bytes File Registers RAM Addr 9
10 Instruction Reg Direct Addr 5
Addr MUX 5-7 Indirect Addr RC0 RC1 RC2 RC3 RC4 RC5 C1IN+ C1INC1OUT
FSR Reg STATUS Reg 8 3 Device Reset Timer Instruction Decode & Control Timing Generation Power-on Reset Watchdog Timer Internal RC Clock 8 W Reg ALU Comparator 2 Comparator 1 MUX VREF
C2IN+ C2INC2OUT CVREF CVREF CVREF
OSC1/CLKIN OSC2/CLKOUT
Timer0 AN0 MCLR VDD, VSS 8-bit ADC AN1 AN2
T0CKI
VREF
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TABLE 3-3:
Name RB0/AN0/C1IN+/ICSPDAT
PIN DESCRIPTIONS - PIC16F506
Function RB0 Input Type TTL Output Type CMOS Description Bidirectional I/O port. Can be software programmed for internal weak pull-up and wake-up from Sleep on pin change. ADC channel input. Comparator 1 input. In-Circuit Serial Programming data pin. Bidirectional I/O port. Can be software programmed for internal weak pull-up and wake-up from Sleep on pin change. ADC channel input. Comparator 1 input. In-Circuit Serial Programming clock pin. Bidirectional I/O port. ADC channel input. Comparator 1 output. Standard TTL input. Can be software programmed for internal weak pull-up and wake-up from Sleep on pin change. MCLR input - weak pull-up always enabled in this mode. Programming voltage input. Bidirectional I/O port. Can be software programmed for internal weak pull-up and wake-up from Sleep on pin change. XTAL oscillator output pin. EXTRC/INTOSC CLKOUT pin (FOSC/4). Bidirectional I/O port. XTAL oscillator input pin. EXTRC/EC Schmitt Trigger input. Bidirectional I/O port. Comparator 2 input. Bidirectional I/O port. Comparator 2 input. Bidirectional I/O port. Programmable Voltage Reference output. Bidirectional I/O port. Bidirectional I/O port. Comparator 2 output. Bidirectional I/O port. Timer0 clock input. Positive supply for logic and I/O pins. Ground reference for logic and I/O pins.
AN0 C1IN+ ICSPDAT RB1/AN1/C1IN-/ICSPCLK RB1
AN AN ST TTL
-- -- CMOS CMOS
AN1 C1INICSPCLK RB2/AN2/C1OUT RB2 AN2 C1OUT RB3/MCLR/VPP RB3
AN AN ST TTL AN -- TTL
-- -- -- CMOS -- CMOS --
MCLR VPP RB4/OSC2/CLKOUT RB4
ST High Voltage TTL
-- -- CMOS
OSC2 CLKOUT RB5/OSC1/CLKIN RB5 OSC1 CLKIN RC0/C2IN+ RC1/C2INRC2/CVREF RC3 RC4/C2OUT RC5/T0CKI VDD VSS RC0 C2IN+ RC1 C2INRC2 CVREF RC3 RC4 C2OUT RC5 T0CKI VDD VSS
-- -- TTL XTAL ST TTL AN TTL AN TTL -- TTL TTL -- TTL ST P P
XTAL CMOS CMOS -- -- CMOS -- CMOS -- CMOS AN CMOS CMOS CMOS CMOS -- -- --
Legend: I = input, O = output, I/O = input/output, P = power, -- = Not Used, TTL = TTL input, ST = Schmitt Trigger input, AN = Analog Voltage
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3.1 Clocking Scheme/Instruction Cycle 3.2 Instruction Flow/Pipelining
An instruction cycle consists of four Q cycles (Q1, Q2, Q3 and Q4). The instruction fetch and execute are pipelined such that fetch takes one instruction cycle, while decode and execute take another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the PC to change (e.g., GOTO), then two cycles are required to complete the instruction (Example 3-1). A fetch cycle begins with the PC incrementing in Q1. In the execution cycle, the fetched instruction is latched into the Instruction Register (IR) in cycle Q1. This instruction is then decoded and executed during the Q2, Q3 and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write).
The clock input (OSC1/CLKIN pin) is internally divided by four to generate four non-overlapping quadrature clocks, namely Q1, Q2, Q3 and Q4. Internally, the PC is incremented every Q1 and the instruction is fetched from program memory and latched into the instruction register in Q4. It is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow is shown in Figure 3-3 and Example 3-1.
FIGURE 3-3:
CLOCK/INSTRUCTION CYCLE
Q1 OSC1 Q1 Q2 Q3 Q4 PC PC Fetch INST (PC) Execute INST (PC - 1) PC + 1 PC + 2 Internal Phase Clock Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Fetch INST (PC + 1) Execute INST (PC)
Fetch INST (PC + 2) Execute INST (PC + 1)
EXAMPLE 3-1:
1. MOVLW 03H 2. MOVWF PORTB 3. CALL SUB_1
INSTRUCTION PIPELINE FLOW
Fetch 1 Execute 1 Fetch 2 Execute 2 Fetch 3 Execute 3 Fetch 4 Flush Fetch SUB_1 Execute SUB_1
4. BSF PORTB, BIT1
All instructions are single cycle, except for any program branches. These take two cycles, since the fetch instruction is "flushed" from the pipeline, while the new instruction is being fetched and then executed.
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PIC12F510/16F506
4.0 MEMORY ORGANIZATION
FIGURE 4-1:
The PIC12F510/16F506 memories are organized into program memory and data memory. For devices with more than 512 bytes of program memory, a paging scheme is used. Program memory pages are accessed using STATUS register bit PA0. For the PIC12F510 and PIC16F506, with data memory register files of more than 32 registers, a banking scheme is used. Data memory banks are accessed using the File Select Register (FSR).
PROGRAM MEMORY MAP AND STACK FOR THE PIC12F510/16F506
PC<11:0> 10 Stack Level 1 Stack Level 2
CALL, RETLW
Reset Vector(1)
0000h
4.1
Program Memory Organization for the PIC12F510/16F506
User Memory Space
The PIC12F510/16F506 devices have a 10-bit Program Counter (PC) capable of addressing a 2K x 12 program memory space. Only the first 1K x 12 (0000h-03FFh) are physically implemented (see Figure 4-1). Accessing a location above these boundaries will cause a wraparound within the 1K x 12 space. The effective Reset vector is a 0000h (see Figure 4-1). Location 03FFh contains the internal clock oscillator calibration value. This value should never be overwritten.
On-chip Program Memory
512 Word
01FFh 0200h
On-chip Program Memory
1024 Word
03FFh 0400h
7FFh Note 1: Address 0000h becomes the effective Reset vector. Location 03FFh contains the MOVLW XX internal oscillator calibration value.
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PIC12F510/16F506
4.2 Data Memory Organization
FIGURE 4-2:
FSR<5> File Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Fh 10h General Purpose Registers INDF(1) TMR0 PCL STATUS FSR OSCCAL GPIO CM1CON0 ADCON0 ADRES General Purpose Registers Addresses map back to addresses in Bank 0.
Data memory is composed of registers or bytes of RAM. Therefore, data memory for a device is specified by its register file. The register file is divided into two functional groups: Special Function Registers (SFR) and General Purpose Registers (GPR). The Special Function Registers include the TMR0 register, the Program Counter (PCL), the STATUS register, the I/O registers (ports) and the File Select Register (FSR). In addition, Special Function Registers are used to control the I/O port configuration and prescaler options. The General Purpose Registers are used for data and control information under command of the instructions. For the PIC12F510, the register file is composed of 10 Special Function Registers, 6 General Purpose Registers and 32 General Purpose Registers accessed by banking (see Figure 4-2). For the PIC16F506, the register file is composed of 13 Special Function Registers, 3 General Purpose Registers and 64 General Purpose Registers accessed by banking (see Figure 4-3).
PIC12F510 REGISTER FILE MAP
0 1
20h
2Fh
30h General Purpose Registers
4.2.1
GENERAL PURPOSE REGISTER FILE
1Fh Bank 0 Note 1: Not a physical register. 3Fh Bank 1
The General Purpose Register file is accessed either directly or indirectly through the File Select Register (FSR). See Section 4.8 "Indirect Data Addressing: INDF and FSR Registers".
FIGURE 4-3:
FSR<6:5>
PIC16F506 REGISTER FILE MAP
00 INDF(1) TMR0 PCL STATUS FSR OSCCAL PORTB PORTC CM1CON0 ADCON0 ADRES CM2CON0 VRCON 20h 01 40h 10 60h 11
File Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Fh 10h
Addresses map back to addresses in Bank 0.
General Purpose Registers General Purpose Registers
Bank 0
2Fh 30h
4Fh
6Fh
General Purpose Registers
Bank 1
50h
General Purpose Registers
Bank 2
70h
General Purpose Registers
Bank 3
1Fh
3Fh
5Fh
7Fh
Note 1: Not a physical register.
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Preliminary
(c) 2006 Microchip Technology Inc.
PIC12F510/16F506
4.2.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers (SFRs) are registers used by the CPU and peripheral functions to control the operation of the device (see Table 4-1). The Special Function Registers can be classified into two sets. The Special Function Registers associated with the "core" functions are described in this section. Those related to the operation of the peripheral features are described in the section for each peripheral feature.
TABLE 4-1:
Address N/A N/A 00h 01h 02h(1) 03h 04h 05h 06h 07h 08h 09h Legend: Note 1:
SPECIAL FUNCTION REGISTER SUMMARY - PIC12F510
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-on Reset --11 1111 1111 1111 xxxx xxxx xxxx xxxx 1111 1111 PA0 TO PD Z DC C 0001 1xxx 100x xxxx CAL3 GP4 C1T0CS ADCS0 CAL2 GP3 C1ON CHS1 CAL1 GP2 C1NREF CHS0 CAL0 GP1 C1PREF GO/DONE -- GP0 C1WU ADON 1111 111--xx xxxx 1111 1111 1111 1100 xxxx xxxx
TRIS OPTION INDF TMR0 PCL STATUS FSR OSCCAL GPIO CM1CON0 ADCON0 ADRES
I/O Control Registers (TRISGPIO) Contains control bits to configure Timer0 and Timer0/WDT Prescaler Uses contents of FSR to address data memory (not a physical register) Timer0 Module Register Low Order 8 bits of PC GPWUF CWUF
Indirect Data Memory Address Pointer CAL6 -- C1OUT ANS1 CAL5 -- C1OUTEN ANS0 CAL4 GP5 C1POL ADCS1
ADC Conversion Result
x = unknown, u = unchanged, - = unimplemented, read as `0' (if applicable). Shaded cells = unimplemented or unused. The upper byte of the Program Counter is not directly accessible. See Section 4.6 "Program Counter" for an explanation of how to access these bits.
TABLE 4-2:
Address N/A N/A 00h 01h 02h(1) 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch Legend: Note 1:
SPECIAL FUNCTION REGISTER SUMMARY - PIC16F506
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-on Reset --11 1111 1111 1111 xxxx xxxx xxxx xxxx 1111 1111 PA0 CAL4 RB5 RC5 C1POL ADCS1 TO CAL3 RB4 RC4 C1T0CS ADCS0 PD CAL2 RB3 RC3 C1ON CHS1 Z CAL1 RB2 RC2 C1NREF CHS0 DC CAL0 RB1 RC1 C1PREF GO/DONE C -- RB0 RC0 C1WU ADON 0001 1xxx 100x xxxx 1111 111--xx xxxx --xx xxxx 1111 1111 1111 1100 xxxx xxxx C2POL VRR C2PREF2 -- C2ON VR3 C2NREF VR2 C2PREF1 VR1 C2WU VR0 1111 1111 001- 1111
Name TRIS OPTION INDF TMR0 PCL STATUS FSR OSCCAL PORTB PORTC CM1CON0 ADCON0 ADRES CM2CON0 VRCON
I/O Control Registers (TRISB, TRISC) Contains control bits to configure Timer0 and Timer0/WDT Prescaler Uses contents of FSR to address data memory (not a physical register) Timer0 Module Register Low Order 8 bits of PC RBWUF CAL6 -- -- C1OUT ANS1 CWUF CAL5 -- -- C1OUTEN ANS0
Indirect Data Memory Address Pointer
ADC Conversion Result C2OUT VREN C2OUTEN VROE
x = unknown, u = unchanged, - = unimplemented, read as `0' (if applicable). Shaded cells = unimplemented or unused. The upper byte of the Program Counter is not directly accessible. See Section 4.6 "Program Counter" for an explanation of how to access these bits.
(c) 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 17
PIC12F510/16F506
4.3 STATUS Register
This register contains the arithmetic status of the ALU, the Reset status and the page preselect bit. The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. For example, CLRF STATUS, will clear the upper three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged). Therefore, it is recommended that only BCF, BSF and MOVWF instructions be used to alter the STATUS register. These instructions do not affect the Z, DC or C bits from the STATUS register. For other instructions which do affect Status bits, see Section 11.0 "Instruction Set Summary".
REGISTER 4-1:
STATUS REGISTER (ADDRESS: 03h) (PIC12F510)
R/W-0 GPWUF bit 7 R/W-0 CWUF R/W-0 PA0 R-1 TO R-1 PD R/W-X Z R/W-X DC R/W-X C bit 0
bit 7
GPWUF: GPIO Reset bit 1 = Reset due to wake-up from Sleep on pin change 0 = After power-up or other Reset CWUF: Comparator Reset bit 1 = Reset due to wake-up from Sleep on comparator change 0 = After power-up or other Reset PA0: Program Page Preselect bit 1 = Page 1 (200h-3FFh) 0 = Page 0 (000h-1FFh) Each page is 512 bytes. Using the PA0 bit as a general purpose read/write bit in devices which do not use it for program page preselect is not recommended, since this may affect upward compatibility with future products. TO: Time-out bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero DC: Digit carry/borrow bit (for ADDWF and SUBWF instructions) ADDWF: 1 = A carry from the 4th low-order bit of the result occurred 0 = A carry from the 4th low-order bit of the result did not occur SUBWF: 1 = A borrow from the 4th low-order bit of the result did not occur 0 = A borrow from the 4th low-order bit of the result occurred C: Carry/borrow bit (for ADDWF, SUBWF and RRF, RLF instructions) ADDWF: SUBWF: RRF or RLF: 1 = A carry occurred 1 = A borrow did not occur Load bit with LSb or MSb, respectively 0 = A carry did not occur 0 = A borrow occurred Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
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PIC12F510/16F506
REGISTER 4-2: STATUS REGISTER (ADDRESS: 03h) (PIC16F506)
R/W-0 RBWUF bit 7 bit 7 RBWUF: PORTB Reset bit 1 = Reset due to wake-up from Sleep on pin change 0 = After power-up or other Reset CWUF: Comparator Reset bit 1 = Reset due to wake-up from Sleep on comparator change 0 = After power-up or other Reset PA0: Program Page Preselect bits 1 = Page 1 (200h-3FFh) 0 = Page 0 (000h-1FFh) Each page is 512 bytes. Using the PA0 bit as a general purpose read/write bit in devices which do not use it for program page preselect is not recommended, since this may affect upward compatibility with future products. TO: Time-out bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero DC: Digit carry/borrow bit (for ADDWF and SUBWF instructions) ADDWF: 1 = A carry from the 4th low-order bit of the result occurred 0 = A carry from the 4th low-order bit of the result did not occur SUBWF: 1 = A borrow from the 4th low-order bit of the result did not occur 0 = A borrow from the 4th low-order bit of the result occurred C: Carry/borrow bit (for ADDWF, SUBWF and RRF, RLF instructions) ADDWF: SUBWF: RRF or RLF: 1 = A carry occurred 1 = A borrow did not occur Load bit with LSb or MSb, respectively 0 = A carry did not occur 0 = A borrow occurred Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 CWUF R/W-0 PA0 R-1 TO R-1 PD R/W-X Z R/W-X DC R/W-X C bit 0
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
(c) 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 19
PIC12F510/16F506
4.4 OPTION Register
The OPTION register is a 8-bit wide, write-only register, that contains various control bits to configure the Timer0/WDT prescaler and Timer0. By executing the OPTION instruction, the contents of the W register will be transferred to the OPTION register. A Reset sets the OPTION<7:0> bits. Note 1: If TRIS bit is set to `0', the wake-up on change and pull-up functions are disabled for that pin (i.e., note that TRIS overrides Option control of GPPU/RBPU and GPWU/RBWU). 2: If the T0CS bit is set to `1', it will override the TRIS function on the T0CKI pin.
REGISTER 4-3:
OPTION REGISTER (PIC12F510)
W-1 GPWU bit 7 W-1 GPPU W-1 T0CS W-1 T0SE W-1 PSA W-1 PS2 W-1 PS1 W-1 PS0 bit 0
bit 7
GPWU: Enable Wake-up On Pin Change bit (GP0, GP1, GP3) 1 = Disabled 0 = Enabled GPPU: Enable Weak Pull-ups bit (GP0, GP1, GP3) 1 = Disabled 0 = Enabled T0CS: Timer0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (CLKOUT) T0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin PSA: Prescaler Assignment bit 1 = Prescaler assigned to the WDT 0 = Prescaler assigned to Timer0 PS<2:0>: Prescaler Rate Select bits
bit 6
bit 5
bit 4
bit 3
bit 2-0
Bit Value 000 001 010 011 100 101 110 111
Timer0 Rate 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256
WDT Rate 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128
Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
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PIC12F510/16F506
REGISTER 4-4: OPTION REGISTER (PIC16F506)
W-1 RBWU bit 7 bit 7 RBWU: Enable Wake-up On Pin Change bit (RB0, RB1, RB3, RB4) 1 = Disabled 0 = Enabled RBPU: Enable Weak Pull-ups bit (RB0, RB1, RB3, RB4) 1 = Disabled 0 = Enabled T0CS: Timer0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (CLKOUT) T0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin PSA: Prescaler Assignment bit 1 = Prescaler assigned to the WDT 0 = Prescaler assigned to Timer0 PS<2:0>: Prescaler Rate Select bits W-1 RBPU W-1 T0CS W-1 T0SE W-1 PSA W-1 PS2 W-1 PS1 W-1 PS0 bit 0
bit 6
bit 5
bit 4
bit 3
bit 2-0
Bit Value 000 001 010 011 100 101 110 111
Timer0 Rate 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256
WDT Rate 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128
Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
(c) 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 21
PIC12F510/16F506
4.5 OSCCAL Register
The Oscillator Calibration (OSCCAL) register is used to calibrate the internal precision 4/8 MHz oscillator. It contains seven bits for calibration. Note: Erasing the device will also erase the preprogrammed internal calibration value for the internal oscillator. The calibration value must be read prior to erasing the part so it can be reprogrammed correctly later.
After you move in the calibration constant, do not change the value. See Section 10.2.5 "Internal 4/8 MHz RC Oscillator".
REGISTER 4-5:
OSCCAL REGISTER (ADDRESS: 05h)
R/W-1 CAL6 bit 7 R/W-1 CAL5 R/W-1 CAL4 R/W-1 CAL3 R/W-1 CAL2 R/W-1 CAL1 R/W-1 CAL0 U-0 -- bit 0
bit 7-1
CAL<6:0>: Oscillator Calibration bits 0111111 = Maximum frequency * * * 0000001 0000000 = Center frequency 1111111 * * * 1000000 = Minimum frequency Unimplemented: Read as `0' Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 0
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Preliminary
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PIC12F510/16F506
4.6 Program Counter
4.6.1 EFFECTS OF RESET
As a program instruction is executed, the Program Counter (PC) will contain the address of the next program instruction to be executed. The PC value is increased by one every instruction cycle, unless an instruction changes the PC. For a GOTO instruction, bits 8:0 of the PC are provided by the GOTO instruction word. The Program Counter (PCL) is mapped to PC<7:0>. Bit 5 of the STATUS register provides page information to bit 9 of the PC (Figure 4-4). For a CALL instruction, or any instruction where the PCL is the destination, bits 7:0 of the PC again are provided by the instruction word. However, PC<8> does not come from the instruction word, but is always cleared (Figure 4-4). Instructions where the PCL is the destination or modify PCL instructions include MOVWF PC, ADDWF PC and BSF PC, 5. Note: Because PC<8> is cleared in the CALL instruction or any modify PCL instruction, all subroutine calls or computed jumps are limited to the first 256 locations of any program memory page (512 words long). The PC is set upon a Reset, which means that the PC addresses the last location in the last page (i.e., the oscillator calibration instruction). After executing MOVLW XX, the PC will roll over to location 00h and begin executing user code. The STATUS register page preselect bits are cleared upon a Reset, which means that page 0 is preselected. Therefore, upon a Reset, a GOTO instruction will automatically cause the program to jump to page 0 until the value of the page bits is altered.
4.7
Stack
The PIC12F510/16F506 devices have a 2-deep, 12-bit wide hardware PUSH/POP stack. A CALL instruction will PUSH the current value of Stack 1 into Stack 2 and then PUSH the current PC value, incremented by one, into Stack Level 1. If more than two sequential CALLs are executed, only the most recent two return addresses are stored. A RETLW instruction will POP the contents of Stack Level 1 into the PC and then copy Stack Level 2 contents into Stack Level 1. If more than two sequential RETLWs are executed, the stack will be filled with the address previously stored in Stack Level 2. Note 1: The W register will be loaded with the literal value specified in the instruction. This is particularly useful for the implementation of data look-up tables within the program memory. 2: There are no Status bits to indicate stack overflows or stack underflow conditions. 3: There are no instruction mnemonics called PUSH or POP. These are actions that occur from the execution of the CALL and RETLW instructions.
FIGURE 4-4:
LOADING OF PC BRANCH INSTRUCTIONS
0 PCL
GOTO Instruction 9 87 PC
Instruction Word 7 PA0 0
STATUS CALL or Modify PCL Instruction 9 87 PC PCL Instruction Word Reset to `0' PA0 0 STATUS 0
7
(c) 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 23
PIC12F510/16F506
4.8 Indirect Data Addressing: INDF and FSR Registers
EXAMPLE 4-1: HOW TO CLEAR RAM USING INDIRECT ADDRESSING
0x10 FSR INDF FSR,F FSR,4 NEXT ;initialize pointer ;to RAM ;clear INDF register ;inc pointer ;all done? ;NO, clear next ;YES, continue
The INDF register is not a physical register. Addressing INDF actually addresses the register whose address is contained in the FSR register (FSR is a pointer). This is indirect addressing.
4.8.1
* * * *
INDIRECT ADDRESSING EXAMPLE
Register file 07 contains the value 10h Register file 08 contains the value 0Ah Load the value 07 into the FSR register A read of the INDF register will return the value of 10h * Increment the value of the FSR register by one (FSR = 08) * A read of the INDR register now will return the value of 0Ah. Reading INDF itself indirectly (FSR = 0) will produce 00h. Writing to the INDF register indirectly results in a no operation (although Status bits may be affected). A simple program to clear RAM locations 10h-1Fh using indirect addressing is shown in Example 4-1.
MOVLW MOVWF NEXT CLRF INCF BTFSC GOTO CONTINUE : :
The FSR is a 5-bit wide register. It is used in conjunction with the INDF register to indirectly address the data memory area. The FSR<4:0> bits are used to select data memory addresses 00h to 1Fh. PIC16F506 - Uses FSR<6:5>. Selects from Bank 0 to Bank 3. FSR<7> is unimplemented, read as `1'.
PIC12F510 - Uses FSR<5>. Selects from Bank 0 to Bank 1. FSR<7:6> are unimplemented, read as `11'.
FIGURE 4-5:
(FSR) 6 5
DIRECT/INDIRECT ADDRESSING (PIC12F510)
Indirect Addressing (FSR) 0 6 5 4 3 2 1 0
Direct Addressing (opcode) 4 3 2 1
bank select
location select 00 00h Addresses map back to addresses in Bank 0. Data Memory(1) 0Fh 10h 01
bank select
location select
1Fh Bank 0
3Fh Bank 1
Note 1: For register map detail, see Figure 4-2.
DS41268B-page 24
Preliminary
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PIC12F510/16F506
FIGURE 4-6: DIRECT/INDIRECT ADDRESSING (PIC16F506)
Indirect Addressing 6 (FSR) 54321 0 Direct Addressing (FSR) 65 4 (opcode) 3210
Bank Select
Location Select 00 00h 01 10 11 Addresses map back to addresses in Bank 0.
Bank
Location Select
Data Memory(1)
0Fh 10h
1Fh Bank 0 Note 1:
3Fh Bank 1
5Fh Bank 2
7Fh Bank 3
For register map detail, see Figure 4-3.
(c) 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 25
PIC12F510/16F506
NOTES:
DS41268B-page 26
Preliminary
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PIC12F510/16F506
5.0 I/O PORT
5.4 I/O Interfacing
As with any other register, the I/O register(s) can be written and read under program control. However, read instructions (e.g., MOVF PORTB, W) always read the I/O pins independent of the pin's Input/Output modes. On Reset, all I/O ports are defined as input (inputs are at high-impedance) since the I/O control registers are all set. Note: On the PIC12F510, I/O PORTB is referenced as GPIO. On the PIC16F506, I/O PORTB is referenced as PORTB. The equivalent circuit for an I/O port pin is shown in Figure 5-1. All port pins, except RB3/GP3 which is input only, may be used for both input and output operations. For input operations, these ports are non-latching. Any input must be present until read by an input instruction (e.g., MOVF PORTB, W). The outputs are latched and remain unchanged until the output latch is rewritten. To use a port pin as output, the corresponding direction control bit in TRIS must be cleared (= 0). For use as an input, the corresponding TRIS bit must be set. Any I/O pin (except RB3/GP3) can be programmed individually as input or output.
5.1
PORTB/GPIO
FIGURE 5-1: PIC12F510/16F506 EQUIVALENT CIRCUIT FOR PIN DRIVE(2)
PORTB/GPIO is an 8-bit I/O register. Only the loworder 6 bits are used (RB/GP<5:0>). Bits 7 and 6 are unimplemented and read as `0's. Please note that RB3/ GP3 is an input only pin. The Configuration Word can set several I/O's to alternate functions. When acting as alternate functions, the pins will read as `0' during a port read. Pins RB0/GP0, RB1/GP1, RB3/GP3 and RB4 (PIC16F506 only) can be configured with weak pull-up and also for wake-up on change. The wake-up on change and weak pull-up functions are not pin selectable. If RB3/GP3/MCLR is configured as MCLR, weak pull-up is always on and wake-up on change for this pin is not enabled.
Data Bus Data Bus Interface VDD VDD P
(1)
N D Q VSS CK Q VSS
I/O pin
5.2
PORTC (PIC16F506 Only)
PORTC is an 8-bit I/O register. Only the low-order 6 bits are used (RC<5:0>). Bits 7 and 6 are unimplemented and read as `0's.
Reset Note 1: 2: GP3/RB3 has protection diode to VSS only. For pin specific information, see Figure 5-2 through Figure 5-13.
5.3
TRIS Registers
The Output Driver Control register is loaded with the contents of the W register by executing the TRIS f instruction. A `1' from a TRIS register bit puts the corresponding output driver in a High-Impedance mode. A `0' puts the contents of the output data latch on the selected pins, enabling the output buffer. The exception is RB3/GP3, which are input only, and the T0CKI pin, which may be controlled by the OPTION register. See Register 4-3. Note: A read of the port reads the pins, not the output data latches. That is, if an output driver on a pin is enabled and driven high but the external system is holding it low, a read of the port will indicate that the pin is low.
Note:
The TRIS registers are "write-only" and are set (output drivers disabled) upon Reset.
(c) 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 27
PIC12F510/16F506
FIGURE 5-2: BLOCK DIAGRAM OF GP0/RB0 AND GP1/RB1 FIGURE 5-3: BLOCK DIAGRAM OF GP3/RB3 (With Weak Pull-up And Wake-up On Change)
GPPU RBPU GPPU RBPU Data Bus WR Port MCLRE D Data Latch CK Q Reset W Reg Q I/O Pin(1)
D TRIS Latch
Q
I/O Pin(1)
TRIS `f'
CK
Q Data Bus
Reset RD Port ADC pin Ebl COMP pin Ebl Q D
CK RD Port Mis-match Q D
CK
Mis-Match
ADC COMP Note 1: I/O pins have protection diodes to VDD and VSS. Note 1: GP3/MCLR pin has a protection diode to VSS only.
DS41268B-page 28
Preliminary
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PIC12F510/16F506
FIGURE 5-4: BLOCK DIAGRAM OF GP2
C1OUT Data Bus D WR Port Data Latch CK Q Q 0 I/O Pin(1) Data Bus D WR Port Data Latch CK Q Q 1
FIGURE 5-5:
BLOCK DIAGRAM OF RB2
C1OUT 0 I/O Pin(1)
1
C1OUTEN W Reg D TRIS Latch TRIS `f' CK Q TRIS `f' Q W Reg D
C1OUTEN Q TRIS Latch CK Q
Reset T0CS C1T0CS ADC Pin Enable
Reset ADC Pin Enable
RD Port T0CKI
RD Port
ADC ADC
Note 1:
I/O pins have protection diodes to VDD and VSS.
Note 1:
I/O pins have protection diodes to VDD and VSS.
(c) 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 29
PIC12F510/16F506
FIGURE 5-6: BLOCK DIAGRAM OF RB4
RBPU Data Bus Data Bus D WR Port Data Latch CK Q 1 I/O pin(1) W Reg Q 0 WR Port
FIGURE 5-7:
BLOCK DIAGRAM OF GP4
D Data Latch CK
Q I/O pin(1)
Q
D TRIS Latch
Q
W Reg
FOSC/4 TRIS `f' D TRIS Latch Q
CK
Q
TRIS `f'
CK
Q
Reset INTOSC/RC
Reset INTOSC/RC/EC CLKOUT Enable (Note 2) RD Port OSC1 RD Port OSC1 Oscillator Circuit Note 1: I/O pins have protection diodes to VDD and VSS. Oscillator Circuit
Note 1: 2:
I/O pins have protection diodes to VDD and VSS. Input mode is disabled when pin is used for oscillator.
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PIC12F510/16F506
FIGURE 5-8:
Data Bus WR Port
BLOCK DIAGRAM OF RB5/GP5
FIGURE 5-9:
BLOCK DIAGRAM OF RC0/RC1
D Data Latch CK
Q I/O pin(1)
Data Bus WR Port
D Data Latch CK
Q I/O pin(1)
Q
Q
W Reg
D TRIS Latch
Q
W Reg
D TRIS Latch
Q
TRIS `f'
CK
Q
TRIS `f'
CK
Q
Reset (Note 2) Reset Comp Pin Enable
RD Port
OSC2
Oscillator Circuit
RD Port COMP2
Note 1:
I/O pins have protection diodes to VDD and VSS. Note 1: oscillator. I/O pins have protection diodes to VDD and VSS.
2: Input mode is disabled when pin is used for
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Preliminary
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PIC12F510/16F506
FIGURE 5-10: BLOCK DIAGRAM OF RC2
VROE Data Bus CVREF Data Bus WR Port 1 I/O PIN(1) WR Port I/O Pin(1) D Data Latch CK Q Q
FIGURE 5-11:
BLOCK DIAGRAM OF RC3
D Data Latch CK
Q
0 W Reg D TRIS Latch TRIS `f' CK Q Q
Q
W Reg
D TRIS Latch
Q Reset Q
TRIS `f'
CK
Reset
RD Port
RD Port COMP2 Note 1: I/O pins have protection diodes to VDD and VSS. Note 1: I/O pins have protection diodes to VDD and VSS.
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PIC12F510/16F506
FIGURE 5-12: BLOCK DIAGRAM OF RC4
C2OUT Data Bus WR Port 0 I/O Pin(1) Data Bus WR Port I/O Pin(1) D Data Latch CK Q Q
FIGURE 5-13:
BLOCK DIAGRAM OF RC5
D Data Latch CK
Q
1
Q
C2OUTEN W Reg D TRIS Latch TRIS `f' CK Q TRIS `f' Q W Reg D TRIS Latch CK Q T0CS Reset Reset Q
RD Port RD Port Note 1: I/O pins have protection diodes to VDD and VSS. Note 1: T0CKI I/O pins have protection diodes to VDD and VSS.
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Preliminary
DS41268B-page 33
PIC12F510/16F506
TABLE 5-1:
Address N/A N/A N/A N/A N/A 03h 03h 06h 06h 07h Legend: Note 1: 2: 3:
SUMMARY OF PORT REGISTERS
Name Bit 7 -- -- -- GPWU RBWU GPWUF RBWUF -- -- -- Bit 6 -- -- -- GPPU RBPU CWUF CWUF -- -- -- Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-On Reset --11 1111 --11 1111 --11 1111 PSA PSA PD PD GP3 RB3 RC3 PS2 PS2 Z Z GP2 RB2 RC2 PS1 PS1 DC DC GP1 RB1 RC1 PS0 PS0 C C GP0 RB0 RC0 1111 1111 1111 1111 0001 1xxx 0001 1xxx --xx xxxx --xx xxxx --xx xxxx Value on All Other Resets --11 1111 --11 1111 --11 1111 1111 1111 1111 1111 qq0q quuu(3) qq0q quuu(3) --uu uuuu --uu uuuu --uu uuuu
TRISGPIO(1) TRISB(2) TRISC(2) OPTION(1) OPTION
(2)
I/O Control Register I/O Control Register I/O Control Register T0CS T0CS PA0 PA0 GP5 RB5 RC5 TOSE TOSE TO TO GP4 RB4 RC4
STATUS(1) STATUS(2) GPIO(1) PORTB(2) PORTC(2)
- = unimplemented read as `0', x = unknown, u = unchanged, q = depends on condition. PIC12F510 only. PIC16F506 only. If Reset was due to wake-up on pin change, then bit 7 = 1. All other Resets will cause bit 7 = 0.
TABLE 5-2:
Priority 1 2 3
I/O PIN FUNCTION ORDER OF PRECEDENCE (PIC16F506)
RB0 AN0/C1IN+ TRISB -- RB1 AN1/C1INTRISB -- RB2 C1OUT AN2 TRISB RB3 Input/MCLR -- -- RB4 OSC2/CLKOUT TRISB -- RB5 OSC1/CLKIN TRISB --
TABLE 5-3:
Priority 1 2
I/O PIN FUNCTION ORDER OF PRECEDENCE (PIC16F506)
RC0 C2IN+ TRISC RC1 C2INTRISC RC2 CVREF TRISC RC3 TRISC -- RC4 C2OUT TRISC RC5 T0CKI TRISC
TABLE 5-4:
Priority 1 2 3 4
I/O PIN FUNCTION ORDER OF PRECEDENCE (PIC12F510)
GP0 AN0/C1IN+ TRISIO -- -- GP1 AN1/C1INTRISIO -- -- GP2 C1OUT AN2 T0CKI TRISIO GP3 Input/MCLR -- -- -- GP4 OSC2 TRISIO -- -- GP5 OSC1/CLKIN TRISIO -- --
DS41268B-page 34
Preliminary
(c) 2006 Microchip Technology Inc.
PIC12F510/16F506
TABLE 5-5: REQUIREMENTS FOR DIGITAL PIN OPERATION (PIC12F510)
GP0 CM1CON0 C1ON C1PREF C1NREF C1T0CS C1OUTEN CM2CON0 C2ON C2PREF1 C2PREF2 C2NREF C2OUTEN VRCON0 VROE VREN OPTION T0CS ADCON0 ANS<1:0> CONFIG MCLRE INTOSC LP EXTRC XT Note 1: 2: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Disabled -- Disabled -- -- Disabled Disabled Disabled 00, 01 00, 01 00, 01, 10 00, 01, 10 00 00 -- -- -- -- -- -- -- -- 0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0 -- -- -- -- 1 0 -- -- -- 0 -- -- -- -- 1 1 0 -- -- 0 -- -- -- -- 1 -- -- 1 1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- GP0 GP1 GP1 GP2 GP2 GP3 GP4 GP5
Multiple column entries for a pin demonstrate the different permutations to arrive at digital functionality for the pin. Shaded cells indicate the bit status does not affect the pins digital functionality.
(c) 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 35
PIC12F510/16F506
TABLE 5-6:
CM1CON0 C1ON C1PREF C1NREF C1T0CS C1OUTEN CM2CON0 C2ON C2PREF1 C2PREF2 C2NREF C2OUTEN OPTION T0CS ADCON0 ANS<1:0> CONFIG MCLRE INTOSC LP EXTRC XT EC HS INTOSC CLKOUT EXTRC CLOCKOUT Note 1: 2: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- Disabled Disabled 00, 01 00, 01 00, 01 00, 01, 10 00, 01, 10 00 00 -- -- -- -- -- -- -- -- -- -- -- -- -- 1 0 1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0 -- -- -- -- 1 0 -- -- -- 0 -- -- -- -- 1 -- 0 -- -- 0 -- -- -- -- 1 -- -- -- 1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
REQUIREMENTS FOR DIGITAL PIN OPERATION (PIC16F506 PORTB)(1), (2)
RB0 RB0 RB0 RB1 RB1 RB2 RB2 RB3 RB4 RB5
Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled
Multiple column entries for a pin demonstrate the different permutations to arrive at digital functionality for the pin. Shaded cells indicate the bit status does not affect the pins digital functionality.
TABLE 5-7:
CM2CON0 C2ON C2PREF1 C2PREF2 C2NREF
REQUIREMENTS FOR DIGITAL PIN OPERATION (PIC16F506 PORTC)(1), (2)
RC0 0 -- -- -- RC0 1 0 0 -- RC1 0 -- -- -- RC1 1 -- -- 0 RC2 -- -- -- -- RC3 -- -- -- -- RC4 0 -- -- -- RC4 1 -- -- -- RC5 -- -- -- -- RC5 -- -- -- --
-- -- -- -- -- -- -- 1 -- -- C2OUTEN VRCON0 VROE -- -- -- -- 0 -- -- -- -- -- OPTION T0CS -- -- -- -- -- -- -- -- 0 -- Note 1: Multiple column entries for a pin demonstrate the different permutations to arrive at digital functionality for the pin. 2: Shaded cells indicate the bit status does not affect the pins digital functionality.
DS41268B-page 36
Preliminary
(c) 2006 Microchip Technology Inc.
PIC12F510/16F506
5.5
5.5.1
I/O Programming Considerations
BIDIRECTIONAL I/O PORTS
EXAMPLE 5-1:
READ-MODIFY-WRITE INSTRUCTIONS ON AN I/O PORT(e.g., PIC16F506)
Some instructions operate internally as read followed by write operations. For example, the BCF and BSF instructions read the entire port into the CPU, execute the bit operation and re-write the result. Caution must be used when these instructions are applied to a port where one or more pins are used as input/outputs. For example, a BSF operation on bit 5 of PORTB/GPIO will cause all eight bits of PORTB/GPIO to be read into the CPU, bit 5 to be set and the PORTB/GPIO value to be written to the output latches. If another bit of PORTB/ GPIO is used as a bidirectional I/O pin (say bit `0') and it is defined as an input at this time, the input signal present on the pin itself would be read into the CPU and rewritten to the data latch of this particular pin, overwriting the previous content. As long as the pin stays in the Input mode, no problem occurs. However, if bit `0' is switched into Output mode later on, the content of the data latch may now be unknown. Example 5-1 shows the effect of two sequential Read-Modify-Write instructions (e.g., BCF, BSF, etc.) on an I/O port. A pin actively outputting a high or a low should not be driven from external devices at the same time in order to change the level on this pin ("wired OR", "wired AND"). The resulting high output currents may damage the chip.
;Initial PORTB Settings ;PORTB<5:3> Inputs ;PORTB<2:0> Outputs ; ; PORTB latch ; ---------BCF PORTB, 5 ;--01 -ppp BCF PORTB, 4 ;--10 -ppp MOVLW 007h; TRIS PORTB ;--10 -ppp ; Note:
PORTB pins -----------11 pppp --11 pppp --11 pppp
The user may have expected the pin values to be `--00 pppp'. The 2nd BCF caused RB5 to be latched as the pin value (High).
5.5.2
SUCCESSIVE OPERATIONS ON I/O PORTS
The actual write to an I/O port happens at the end of an instruction cycle. Whereas for reading, the data must be valid at the beginning of the instruction cycle (Figure 5-14). Therefore, care must be exercised if a write followed by a read operation is carried out on the same I/O port. The sequence of instructions should allow the pin voltage to stabilize (load dependent) before the next instruction causes the file to be read into the CPU. Otherwise, the previous state of that pin may be read into the CPU rather than the new state. When in doubt, it is better to separate these instructions with a NOP or another instruction not accessing this I/O port.
FIGURE 5-14:
SUCCESSIVE I/O OPERATION (PIC16F506)
Q1 Q2 Q3 Q4 PC + 3 NOP This example shows a write to PORTB followed by a read from PORTB. Data setup time = (0.25 TCY - TPD) where: TCY = instruction cycle TPD = propagation delay Port pin written here Port pin sampled here MOVF PORTB,W (Read PORTB) NOP Therefore, at higher clock frequencies, a write followed by a read may be problematic.
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC Instruction Fetched RB<5:0> MOVWF PORTB PC + 1 MOVF PORTB, W PC + 2 NOP
Instruction Executed
MOVWF PORTB (Write to PORTB)
(c) 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 37
PIC12F510/16F506
NOTES:
DS41268B-page 38
Preliminary
(c) 2006 Microchip Technology Inc.
PIC12F510/16F506
6.0 TMR0 MODULE AND TMR0 REGISTER
The second Counter mode uses the output of the comparator to increment Timer0. It can be entered in two different ways. The first way is selected by setting the T0CS bit (OPTION<5>), and clearing the C1T0CS bit (CM1CON0<4>) (C1OUTEN [CM1CON0<6>] does not affect this mode of operation). This enables an internal connection between the comparator and the Timer0. The second way is selected by setting the T0CS bit (OPTION<5>), setting the C1T0CS bit (CM1CON0) and clearing the C1OUTEN bit (CM1CON0<6>). This allows the output of the comparator onto the T0CKI pin, while keeping the T0CKI input active. Therefore, any comparator change on the COUT pin is fed back into the T0CKI input. The T0SE bit (OPTION<4>) determines the source edge. Clearing the T0SE bit selects the rising edge. Restrictions on the external clock input as discussed in Section 6.1 "Using Timer0 With An External Clock". The prescaler may be used by either the Timer0 module or the Watchdog Timer, but not both. The prescaler assignment is controlled in software by the control bit PSA (OPTION<3>). Clearing the PSA bit will assign the prescaler to Timer0. The prescaler is not readable or writable. When the prescaler is assigned to the Timer0 module, prescale values of 1:2, 1:4,..., 1:256 are selectable. Section 6.2 "Prescaler" details the operation of the prescaler. A summary of registers associated with the Timer0 module is found in Table 6-1.
The Timer0 module has the following features: * * * * 8-bit timer/counter register, TMR0 Readable and writable 8-bit software programmable prescaler Internal or external clock select: - Edge select for external clock - External clock from either the T0CKI pin or from the output of the comparator
Figure 6-1 is a simplified block diagram of the Timer0 module. Timer mode is selected by clearing the T0CS bit (OPTION<5>). In Timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If TMR0 register is written, the increment is inhibited for the following two cycles (Figure 6-2 and Figure 6-3). The user can work around this by writing an adjusted value to the TMR0 register. There are two types of Counter mode. The first Counter mode uses the T0CKI pin to increment Timer0. It is selected by setting the T0CKI bit (OPTION<5>), setting the C1T0CS bit (CM1CON0<4>) and setting the C1OUTEN bit (CM1CON0<6>). In this mode, Timer0 will increment either on every rising or falling edge of pin T0CKI. The T0SE bit (OPTION<4>) determines the source edge. Clearing the T0SE bit selects the rising edge. Restrictions on the external clock input are discussed in detail in Section 6.1 "Using Timer0 With An External Clock".
FIGURE 6-1:
T0CKI Pin
TIMER0 BLOCK DIAGRAM
Data Bus FOSC/4 0 1 1 Programmable Prescaler(2) 3 C1T0CS(3) T0CS(1) PS2, PS1, PS0(1) PSA(1) 0 PSOUT Sync with Internal Clocks 8 TMR0 Reg
Internal Comparator Output
1 0 T0SE(1)
PSOUT (2 TCY delay) Sync
Note 1: 2: 3:
Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in the OPTION register. The prescaler is shared with the Watchdog Timer (Figure 6-5). Bit C1T0CS is located in the CM1CON0 register, CM1CON0<4>.
(c) 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 39
PIC12F510/16F506
FIGURE 6-2: TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE
PC (Program Counter) Instruction Fetch
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC - 1 PC MOVWF TMR0 PC + 1 PC + 2 PC + 3 PC + 4 PC + 5 PC + 6
MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
Timer0 Instruction Executed
T0
T0 + 1
T0 + 2
NT0
NT0 + 1
NT0 + 2
Write TMR0 executed
Read TMR0 reads NT0
Read TMR0 reads NT0
Read TMR0 reads NT0
Read TMR0 Read TMR0 reads NT0 + 1 reads NT0 + 2
FIGURE 6-3:
TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2
PC (Program Counter) Instruction Fetch
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC - 1 PC MOVWF TMR0 PC + 1 PC + 2 PC + 3 PC + 4 PC + 5 PC + 6
MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
Timer0 Instruction Executed
T0
T0 + 1
NT0
NT0 + 1
Write TMR0 executed
Read TMR0 reads NT0
Read TMR0 reads NT0
Read TMR0 reads NT0
Read TMR0 Read TMR0 reads NT0 + 1 reads NT0 + 2
TABLE 6-1:
Addr 01h 07h
08h
REGISTERS ASSOCIATED WITH TIMER0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-On Reset Value on All Other Resets
Name TMR0
CM1CON0(2) CM1CON0
(3)
Timer0 - 8-bit Real-Time Clock/Counter
C1OUT C1OUT C1OUTEN C1OUTEN C1POL C1POL C1T0CS C1T0CS C1ON C1ON C1NREF C1NREF C1PREF C1PREF C1WU C1WU
xxxx xxxx uuuu uuuu
1111 1111
uuuu uuuu
1111 1111 uuuu uuuu
N/A N/A
OPTION TRISGPIO(1)
GPWU --
GPPU --
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111 1111 1111 ---- 1111 --11 1111
I/O Control Register
Legend: Shaded cells not used by Timer0, - = unimplemented, x = unknown, u = unchanged. Note 1: The TRIS of the T0CKI pin is overridden when T0CS = 1. 2: 3: For PIC12F510. For PIC16F506.
DS41268B-page 40
Preliminary
(c) 2006 Microchip Technology Inc.
PIC12F510/16F506
6.1 Using Timer0 With An External Clock
When a prescaler is used, the external clock input is divided by the asynchronous ripple counter-type prescaler, so that the prescaler output is symmetrical. For the external clock to meet the sampling requirement, the ripple counter must be taken into account. Therefore, it is necessary for T0CKI or the comparator output to have a period of at least 4TOSC (and a small RC delay of 4Tt0H) divided by the prescaler value. The only requirement on T0CKI or the comparator output high and low time is that they do not violate the minimum pulse width requirement of Tt0H. Refer to parameters 40, 41 and 42 in the electrical specification of the desired device.
When an external clock input is used for Timer0, it must meet certain requirements. The external clock requirement is due to internal phase clock (TOSC) synchronization. Also, there is a delay in the actual incrementing of Timer0 after synchronization.
6.1.1
EXTERNAL CLOCK SYNCHRONIZATION
When no prescaler is used, the external clock input is the same as the prescaler output. The synchronization of an external clock with the internal phase clocks is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks (Figure 6-4). Therefore, it is necessary for T0CKI or the comparator output to be high for at least 2TOSC (and a small RC delay of 2Tt0H) and low for at least 2TOSC (and a small RC delay of 2Tt0H). Refer to the electrical specification of the desired device.
6.1.2
TIMER0 INCREMENT DELAY
Since the prescaler output is synchronized with the internal clocks, there is a small delay from the time the external clock edge occurs to the time the Timer0 module is actually incremented. Figure 6-4 shows the delay from the external clock edge to the timer incrementing.
FIGURE 6-4:
TIMER0 TIMING WITH EXTERNAL CLOCK
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Small pulse misses sampling
External Clock Input or Prescaler Output(2) (1) External Clock/Prescaler Output After Sampling Increment Timer0 (Q4) Timer0 T0 T0 + 1 (3)
T0 + 2
Note 1: 2: 3:
Delay from clock input change to Timer0 increment is 3TOSC to 7TOSC. (Duration of Q = TOSC). Therefore, the error in measuring the interval between two edges on Timer0 input = 4TOSC max. External clock if no prescaler selected; prescaler output otherwise. The arrows indicate the points in time where sampling occurs.
6.2
Prescaler
An 8-bit counter is available as a prescaler for the Timer0 module or as a postscaler for the Watchdog Timer (WDT), respectively (see Figure 10-12). For simplicity, this counter is being referred to as "prescaler" throughout this data sheet. Note: The prescaler may be used by either the Timer0 module or the WDT, but not both. Thus, a prescaler assignment for the Timer0 module means that there is no prescaler for the WDT and vice-versa.
When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g., CLRF 1, MOVWF 1, BSF 1, x, etc.) will clear the prescaler. When assigned to WDT, a CLRWDT instruction will clear the prescaler along with the WDT. The prescaler is neither readable nor writable. On a Reset, the prescaler contains all `0's.
The PSA and PS<2:0> bits (OPTION<3:0>) determine prescaler assignment and prescale ratio.
(c) 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 41
PIC12F510/16F506
6.2.1 SWITCHING PRESCALER ASSIGNMENT
The prescaler assignment is fully under software control (i.e., it can be changed "on-the-fly" during program execution). To avoid an unintended device Reset, the following instruction sequence (Example 6-1) must be executed when changing the prescaler assignment from Timer0 to the WDT. To change prescaler from the WDT to the Timer0 module, use the sequence shown in Example 6-2. This sequence must be used even if the WDT is disabled. A CLRWDT instruction should be executed before switching the prescaler.
EXAMPLE 6-2:
CLRWDT
CHANGING PRESCALER (WDTTIMER0)
;Clear WDT and ;prescaler ;Select TMR0, new ;prescale value and ;clock source
EXAMPLE 6-1:
CLRWDT CLRF TMR0 MOVLW `00xx1111'b OPTION CLRWDT MOVLW `00xx1xxx'b OPTION
CHANGING PRESCALER (TIMER0 WDT)
;Clear WDT ;Clear TMR0 & Prescaler ;These 3 lines (5, 6, 7) ;are required only if ;desired ;PS<2:0> are 000 or 001 ;Set Postscaler to ;desired WDT rate
MOVLW
`xxxx0xxx'
OPTION
FIGURE 6-5:
T0CKI(2) Pin
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
TCY (= FOSC/4) Data Bus 0 M U X 8 1 0 T0SE(1) M U X Sync 2 Cycles TMR0 Reg
Comparator Output
1 1 0
T0CS(1)
PSA(1)
C1T0CS(3) 0 M U X 8-bit Prescaler 8 8-to-1 MUX PSA(1) WDT Enable bit 0 MUX 1 PSA(1) PS<2:0>(1)
Watchdog Timer
1
WDT Time-Out Note 1: 2: 3: T0CS, T0SE, PSA, PS<2:0> are bits in the OPTION register. T0CKI is shared with pin GP2 on the PIC12F510 and shared with RC5 on the PIC16F506. Bit C1T0CS is located in the CM1CON0 register.
DS41268B-page 42
Preliminary
(c) 2006 Microchip Technology Inc.
PIC12F510/16F506
7.0 COMPARATOR(S)
The PIC12F510 contains one analog comparator module. The PIC16F506 contains two comparators and a comparator voltage reference.
REGISTER 7-1:
CM1CON0 REGISTER (ADDRESS: 07h) (PIC12F510)
R-1 C1OUT bit 7 R/W-1 C1OUTEN R/W-1 C1POL R/W-1 C1T0CS R/W-1 C1ON R/W-1 C1NREF R/W-1 C1PREF R/W-1 C1WU bit 0
bit 7
C1OUT: Comparator Output bit 1 = VIN+ > VIN0 = VIN+ < VINC1OUTEN: Comparator Output Enable bit(1), (2) 1 = Output of comparator is NOT placed on the C1OUT pin 0 = Output of comparator is placed in the C1OUT pin C1POL: Comparator Output Polarity bit(2) 1 = Output of comparator is not inverted 0 = Output of comparator is inverted C1T0CS: Comparator TMR0 Clock Source bit(2) 1 = TMR0 clock source selected by T0CS control bit 0 = Comparator output used as TMR0 clock source C1ON: Comparator Enable bit 1 = Comparator is on 0 = Comparator is off C1NREF: Comparator Negative Reference Select bit(2) 1 = C1IN pin 0 = VREF C1PREF: Comparator Positive Reference Select bit(2) 1 = C1IN+ pin 0 = C1IN- pin C1WU: Comparator Wake-up On Change Enable bit(2) 1 = Wake-up On Comparator Change is disabled 0 = Wake-up On Comparator Change is enabled Note 1: Overrides T0CS bit for TRIS control of GP2. 2: When comparator is turned on, these control bits assert themselves. Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
(c) 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 43
PIC12F510/16F506
REGISTER 7-2: CM1CON0 REGISTER (ADDRESS: 08h) (PIC16F506)
R-1 C1OUT bit 7 bit 7 C1OUT: Comparator Output bit 1 = VIN+ > VIN0 = VIN+ < VINC1OUTEN: Comparator Output Enable bit(1), (2) 1 = Output of comparator is NOT placed on the C1OUT pin 0 = Output of comparator is placed in the C1OUT pin C1POL: Comparator Output Polarity bit(2) 1 = Output of comparator not inverted 0 = Output of comparator inverted C1T0CS: Comparator TMR0 Clock Source bit(2) 1 = TMR0 clock source selected by TOCS control bit 0 = Comparator output used as TMR0 clock source C1ON: Comparator Enable bit 1 = Comparator is on 0 = Comparator is off C1NREF: Comparator Negative Reference Select bit(2) 1 = C1IN- pin 0 = VREF C1PREF: Comparator Positive Reference Select bit(2) 1 = C1IN+ pin 0 = C1IN- pin C1WU: Comparator Wake-up On Change Enable bit(2) 1 = Wake-up On Comparator Change is disabled 0 = Wake-up On Comparator Change is enabled. Note 1: Overrides T0CS bit for TRIS control of RC5. 2: When comparator is turned on, these control bits assert themselves. Otherwise, the other registers have precedence. Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 C1OUTEN R/W-1 C1POL R/W-1 C1T0CS R/W-1 C1ON R/W-1 C1NREF R/W-1 C1PREF R/W-1 C1WU bit 0
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DS41268B-page 44
Preliminary
(c) 2006 Microchip Technology Inc.
PIC12F510/16F506
REGISTER 7-3: CM2CON0 REGISTER (ADDRESS: 0Bh) (PIC16F506)
R-1 C2OUT bit 7 bit 7 C2OUT: Comparator Output bit 1 = VIN+ > VIN0 = VIN+ < VINC2OUTEN: Comparator Output Enable bit(1), (2) 1 = Output of comparator is NOT placed on the C2OUT pin 0 = Output of comparator is placed in the C2OUT pin C2POL: Comparator Output Polarity bit(2) 1 = Output of comparator not inverted 0 = Output of comparator inverted C2PREF2: Comparator Positive Reference Select bit(2) 1 = C1IN+ pin 0 = C2IN- pin C2ON: Comparator Enable bit 1 = Comparator is on 0 = Comparator is off C2NREF: Comparator Negative Reference Select bit(2) 1 = C2IN- pin 0 = VREF C2PREF1: Comparator Positive Reference Select bit(2) 1 = C2IN+ pin 0 = C2PREF2 controls analog input selection C2WU: Comparator Wake-up on Change Enable bit(2) 1 = Wake-up on Comparator change is disabled 0 = Wake-up on Comparator change is enabled. Note 1: Overrides TOCS bit for TRIS control of RC4. 2: When comparator is turned on, these control bits assert themselves. Otherwise, the other registers have precedence. Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 C2OUTEN R/W-1 C2POL R/W-1 C2PREF2 R/W-1 C2ON R/W-1 R/W-1 R/W-1 C2WU bit 0 C2NREF C2PREF1
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
(c) 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 45
PIC12F510/16F506
FIGURE 7-1: COMPARATOR 1 BLOCK DIAGRAM FOR PIC12F510/16F506
C1PREF
To Data Bus
MUX
C1INC1IN+
0
RD_CM1CON0
1 D Q3 * RD_CM1CON0 Q C1WU EN CL NRESET
C1WUF
C1NREF
C1ON(1)
C1 Output Enable C1IN0.6 VREF 1 MUX + C1 C1OUT C1POL Note 1: When C1ON = 0, the comparator, C1, will produce a `0' output to the XOR Gate. C1OUT
0
FIGURE 7-2:
COMPARATOR 2 BLOCK DIAGRAM (PIC16F506 ONLY)
To Data Bus RD_CM2CON0 C2WUF C2WU
C2PREF1 C2PREF2 C2IN+ C1IN+ 1 MUX 0 1 MUX + C2 C2OUT C2ON(1) Q3 * RD_CM2CON0 NRESET
D EN CL
Q
C2IN-
0
C2 Output Enable
C2NREF C2IN1 MUX
C2POL C2OUT
CVREF
0
Note
1:
When C2ON = 0, the comparator, C2, will produce a `0' output to the XOR Gate.
DS41268B-page 46
Preliminary
(c) 2006 Microchip Technology Inc.
PIC12F510/16F506
7.1 Comparator Operation
Note: Analog levels on any pin that is defined as a digital input may cause the input buffer to consume more current than is specified. A single comparator is shown in Figure 7-3 along with the relationship between the analog input levels and the digital output. When the analog input at VIN+ is less than the analog input VIN-, the output of the comparator is a digital low level. The shaded area of the output of the comparator in Figure 7-3 represent the uncertainty due to input offsets and response time. See Table 13-1 for Common Mode Voltage.
7.5
Comparator Wake-up Flag
The Comparator Wake-up Flag is set whenever all of the following conditions are met: * C1WU = 0 (CM1CON0<0>) or C2WU = 0 (CM2CON0<0>) * CM1CON0 or CM2CON0 has been read to latch the last known state of the C1OUT and C2OUT bit (MOVF CM1CON0, W) * Device is in Sleep * The output of a comparator has changed state The wake-up flag may be cleared in software or by another device Reset.
FIGURE 7-3:
SINGLE COMPARATOR
VIN+ VIN-
+ Result -
VINVIN+
7.6
Comparator Operation During Sleep
When the comparator is enabled it is active. To minimize power consumption while in Sleep mode, turn off the comparator before entering Sleep.
Result
7.7
Effects of Reset
7.2
Comparator Reference
An internal reference signal may be used depending on the comparator operating mode. The analog signal that is present at VIN- is compared to the signal at VIN+, and the digital output of the comparator is adjusted accordingly (Figure 7-3). Please see Section 8.0 "Comparator Voltage Reference Module (PIC16F506 only)" for internal reference specifications.
A Power-on Reset (POR) forces the CM2CON0 register to its Reset state. This forces the Comparator input pins to analog Reset mode. Device current is minimized when analog inputs are present at Reset time.
7.8
Analog Input Connection Considerations
7.3
Comparator Response Time
Response time is the minimum time after selecting a new reference voltage or input source before the comparator output is to have a valid level. If the comparator inputs are changed, a delay must be used to allow the comparator to settle to its new state. Please see Table 13-1 for comparator response time specifications.
A simplified circuit for an analog input is shown in Figure 7-4. Since the analog pins are connected to a digital output, they have reverse biased diodes to VDD and VSS. The analog input, therefore, must be between VSS and VDD. If the input voltage deviates from this range by more than 0.6V in either direction, one of the diodes is forward biased and a latch-up may occur. A maximum source impedance of 10 k is recommended for the analog sources. Any external component connected to an analog input pin, such as a capacitor or a Zener diode, should have very little leakage current.
7.4
Comparator Output
The comparator output is read through the CM1CON0 or CM2CON0 register. This bit is read-only. The comparator output may also be used externally, see Figure 7-3.
(c) 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 47
PIC12F510/16F506
FIGURE 7-4: ANALOG INPUT MODE
VDD RS < 10 K AIN VA CPIN 5 pF VT = 0.6V ILEAKAGE 500 nA VT = 0.6V RIC
VSS Legend: CPIN VT ILEAKAGE RIC RS VA = = = = = = Input Capacitance Threshold Voltage Leakage Current at the Pin Interconnect Resistance Source Impedance Analog Voltage
TABLE 7-1:
Add Name
REGISTERS ASSOCIATED WITH COMPARATOR MODULE
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR 0001 1xxx 1111 1111 1111 1111 1111 1111 --11 1111 --11 1111 --11 1111 Value on All Other Resets qq0q quuu uuuu uuuu uuuu uuuu uuuu uuuu --11 1111 --11 1111 --11 1111
03h 07h 08h 0Bh N/A N/A N/A Legend: Note 1: 2:
STATUS CM1CON0
(1)
GPWUF C1OUT C1OUT C2OUT -- -- --
CWUF C1OUTEN C1OUTEN C2OUTEN -- -- --
PA0 C1POL C1POL C2POL
TO C1T0CS C1T0CS C2PREF2
PD C1ON C1ON C2ON
Z C1NREF C1NREF C2NREF
DC C1PREF C1PREF C2PREF1
C C1WU C1WU C2WU
CM1CON0(2) CM2CON0(2) TRISB(2) TRISC(2) TRISGPIO(1)
I/O Control Register I/O Control Register I/O Control Register
x = Unknown, u = Unchanged, - = Unimplemented, read as `0', q = Depends on condition. PIC12F510 only. PIC16F506 only.
DS41268B-page 48
Preliminary
(c) 2006 Microchip Technology Inc.
PIC12F510/16F506
8.0 COMPARATOR VOLTAGE REFERENCE MODULE (PIC16F506 ONLY)
8.2 Voltage Reference Accuracy/Error
The full range of VSS to VDD cannot be realized due to construction of the module. The transistors on the top and bottom of the resistor ladder network (Figure 8-1) keep CVREF from approaching VSS or VDD. The exception is when the module is disabled by clearing the VREN bit (VRCON<7>). When disabled, the reference voltage is VSS when VR<3:0> is `0000' and the VRR (VRCON<5>) bit is set. This allows the comparator to detect a zero-crossing and not consume the CVREF module current. The voltage reference is VDD derived and, therefore, the CVREF output changes with fluctuations in VDD. The tested absolute accuracy of the comparator voltage reference can be found in Section 13.2 "DC Characteristics: PIC12F510/16F506 (Extended)".
The Comparator Voltage Reference module also allows the selection of an internally generated voltage reference for one of the C2 comparator inputs. The VRCON register (Register 8-1) controls the Voltage Reference module shown in Figure 8-1.
8.1
Configuring The Voltage Reference
The voltage reference can output 32 voltage levels; 16 in a high range and 16 in a low range. Equation 8-1 determines the output voltages:
EQUATION 8-1:
VRR = 1 (low range): CVREF = (VR3:VR0/24) x VDD VRR = 0 (high range): CVREF = (VDD/4) + (VR3:VR0 x VDD/32)
REGISTER 8-1:
VRCON: PIC16F506 ONLY (ADDRESS: 0Ch)
R/W-0 VREN bit 7 R/W-0 VROE R/W-1 VRR U-0 -- R/W-1 VR3 R/W-1 VR2 R/W-1 VR1 R/W-1 VR0 bit 0
bit 7
VREN: CVREF Enable bit 1 = CVREF is powered on 0 = CVREF is powered down, no current is drawn VROE: CVREF Output Enable bit(1) 1 = VREF output is enabled 0 = VREF output is disabled VRR: CVREF Range Selection bit 1 = Low range 0 = High range Unimplemented: Read as `0' VR<3:0> CVREF Value Selection bit When VRR = 1: CVREF= (VR<3:0>/24)*VDD When VRR = 0: CVREF= VDD/4+(VR<3:0>/32)*VDD Note 1: When this bit is set, the TRIS for the VREF pin is overridden and the analog voltage is placed on the VREF pin. 2: VREF controls for ratio metric reference applies to Comparator 2 on the PIC12F506 only. Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 6
bit 5
bit 4 bit 3-0
(c) 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 49
PIC12F510/16F506
FIGURE 8-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
16 Stages
8R VDD
R
R
R
R
8R
VRR
VREN CVREF to Comparator 2 Input
16-1 Analog MUX
VR3:VR0 RC2/VREF VROE VREN VR3:VR0 = `0000' VRR
TABLE 8-1:
Add 0Ch 08h 0Bh Name VRCON CM1CON0(1) CM2CON0(1)
REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE
Bit 7 VREN C1OUT C2OUT Bit 6 VROE C1OUTEN C2OUTEN Bit 5 VRR C1POL C2POL Bit 4 -- C1T0CS C2PREF2 Bit 3 VR3 C1ON C2ON Bit 2 VR2 C1NREF C2NREF Bit 1 VR1 C1PREF C2PREF1 Bit 0 VR0 C1WU C2WU Value on POR 001- 1111 1111 1111 1111 1111 Value on all other Resets 001- 1111 uuuu uuuu uuuu uuuu
Legend: Note 1:
x = unknown, u = unchanged, - = unimplemented, read as `0'. PIC16F506 only.
DS41268B-page 50
Preliminary
(c) 2006 Microchip Technology Inc.
PIC12F510/16F506
9.0 ANALOG-TO-DIGITAL (A/D) CONVERTER
Note: It is the users responsibility to ensure that use of the ADC and comparator simultaneously on the same pin, does not adversely affect the signal being monitored or adversely effect device operation.
The A/D Converter allows conversion of an analog signal into an 8-bit digital signal.
9.1
Clock Divisors
The ADC has 4 clock source settings ADCS<1:0>. There are 3 divisor values 32, 16 and 8. The fourth setting is INTOSC with a divisor of 4. These settings will allow a proper conversion when using an external oscillator at speeds from 20 MHz to 350 kHz. Using an external oscillator at a frequency below 350 kHz requires the ADC oscillator setting to be INTOSC/8 for valid ADC results. The ADC requires 13 TAD periods to complete a conversion. The divisor values do not affect the number of TAD periods required to perform a conversion. The divisor values determine the length of the TAD period. When the ADCS<1:0> bits are changed while an ADC conversion is in process, the new ADC clock source will not be selected until the next conversion is started. This clock source selection will be lost when the device enters Sleep. Note: The ADC clock is derived from the instruction clock. The ADCS divisors are then applied to create the ADC clock
When the CHS<1:0> bits are changed during an ADC conversion, the new channel will not be selected until the current conversion is completed. This allows the current conversion to complete with valid results. All channel selection information will be lost when the device enters Sleep.
TABLE 9-1:
CHANNEL SELECT (ADCS) BITS AFTER AN EVENT
ADCS<1:0> 11 CS<1:0> CS<1:0> 11 11
Event MCLR Conversion completed Conversion terminated Power-on Wake from Sleep
9.1.4
THE GO/DONE BIT
9.1.1
VOLTAGE REFERENCE
There is no external voltage reference for the ADC. The ADC reference voltage will always be VDD.
9.1.2
ANALOG MODE SELECTION
The ANS<1:0> bits are used to configure pins for analog input. Upon any Reset, ANS<1:0> defaults to 11. This configures pins AN0, AN1 and AN2 as analog inputs. The comparator output, C1OUT, will override AN2 as an input if the comparator output is enabled. Pins configured as analog inputs are not available for digital output. Users should not change the ANS bits while a conversion is in process. ANS bits are active regardless of the condition of ADON.
The GO/DONE bit is used to determine the status of a conversion, to start a conversion and to manually halt a conversion in process. Setting the GO/DONE bit starts a conversion. When the conversion is complete, the ADC module clears the GO/DONE bit. A conversion can be terminated by manually clearing the GO/DONE bit while a conversion is in process. Manual termination of a conversion may result in a partially converted result in ADRES. The GO/DONE bit is cleared when the device enters Sleep, stopping the current conversion. The ADC does not have a dedicated oscillator, it runs off of the instruction clock. Therefore, no conversion can occur in sleep. The GO/DONE bit cannot be set when ADON is clear.
9.1.3
ADC CHANNEL SELECTION
The CHS bits are used to select the analog channel to be sampled by the ADC. The CHS<1:0> bits can be changed at any time without adversely effecting a conversion. To acquire an analog signal the CHS<1:0> selection must match one of the pin(s) selected by the ANS<1:0> bits. When the ADC is on (ADON = 1) and a channel is selected that is also being used by the comparator, then both the comparator and the ADC will see the analog voltage on the pin.
(c) 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 51
PIC12F510/16F506
9.1.5 SLEEP
This ADC does not have a dedicated ADC clock, and therefore, no conversion in Sleep is possible. If a conversion is underway and a Sleep command is executed, the GO/DONE and ADON bit will be cleared. This will stop any conversion in process and powerdown the ADC module to conserve power. Due to the nature of the conversion process, the ADRES may contain a partial conversion. At least 1 bit must have been converted prior to Sleep to have partial conversion data in ADRES. The ADCS and CHS bits are reset to their default condition; ANS<1:0> = 11 and CHS<1:0> = 11. * For accurate conversions, TAD must meet the following: * 500 ns < TAD < 50 s * TAD = 1/(FOSC/divisor) Shaded areas indicate TAD out of range for accurate conversions. If analog input is desired at these frequencies, use INTOSC/8 for the ADC clock source.
TABLE 9-2:
Source INTOSC FOSC FOSC FOSC
TAD FOR ADCS SETTINGS WITH VARIOUS OSCILLATORS
Divisor 8 8 16 32 20 MHz -- .2 s .4 s .8 s 16 MHz -- .25 s .5 s 1 s 8 MHz 4 MHz 1 MHz .5 s .5 s 1 s 2 s 1 s 1 s 2 s 4 s -- 4 s 8 s 16 s 500 kHz -- 8 s 16 s 32 s 350 kHz -- 11 s 23 s 46 s 200 kHz -- 20 s 40 s 80 s 100 kHz -- 40 s 80 s 160 s 32 kHz -- 125 s 250 s 500 s
ADCS <1:0> 11 10 01 00
TABLE 9-3:
Entering Sleep Wake or Reset
EFFECTS OF SLEEP ON ADCON0
ANS1 ANS0 ADCS1 1 1 ADCS0 1 1 CHS1 1 1 CHS0 1 1 GO/DONE 0 0 ADON 0 0 Unchanged Unchanged 1 1
DS41268B-page 52
Preliminary
(c) 2006 Microchip Technology Inc.
PIC12F510/16F506
9.1.6 ANALOG CONVERSION RESULT REGISTER
The ADRES register contains the results of the last conversion. These results are present during the sampling period of the next analog conversion process. After the sampling period is over, ADRES is cleared (= 0). A `leading one' is then right shifted into the ADRES to serve as an internal conversion complete bit. As each bit weight, starting with the MSB, is converted, the leading one is shifted right and the converted bit is stuffed into ADRES. After a total of 9 right shifts of the `leading one' have taken place, the conversion is complete; the `leading one' has been shifted out and the GO/DONE bit is cleared. If the GO/DONE bit is cleared in software during a conversion, the conversion stops. The data in ADRES is the partial conversion result. This data is valid for the bit weights that have been converted. The position of the `leading one' determines the number of bits that have been converted. The bits that were not converted before the GO/DONE was cleared are unrecoverable.
REGISTER 9-1:
ADCON0 REGISTER
R/W-1 ANS1 bit 7 R/W-1 ANS0 R/W-1 ADCS1 R/W-1 ADCS0 R/W-1 CHS1 R/W-1 CHS0 R/W-0 GO/DONE R/W-0 ADON bit 0
bit 7-6
ANS<1:0>: ADC Analog Input Pin Select bits(1), (2), (3), (6) 00 = No pins configured for analog input 01 = GP2/AN2 configured as an analog input 10 = GP2/AN2 and GP0/AN0 configured as analog inputs 11 = GP2/AN2, GP1/AN1 and GP0/AN0 configured as analog inputs ADCS<1:0>: ADC Conversion Clock Select bits 00 = FOSC/32 01 = FOSC/16 10 = FOSC/8 11 = INTOSC/8 CHS<1:0>: ADC Channel Select bits for PIC16F506(4), (6) 00 = Channel 00 (GP0/AN0) 01 = Channel 01 (GP1/AN1) 10 = Channel 02 (GP2/AN2) 11 = 0.6V absolute voltage reference GO/DONE: ADC Conversion Status bit(5) 1 = ADC conversion in progress. Setting this bit starts an ADC conversion cycle. This bit is automatically cleared by hardware when the ADC is done converting. 0 = ADC conversion completed/not in progress. Manually clearing this bit while a conversion is in process terminates the current conversion. ADON: ADC Enable bit 1 = ADC module is operating 0 = ADC module is shut-off and consumes no power Note 1: 2: On the PIC16F506, the term is RBx, on PIC12F510, the term is GPx. When the ANS bits are set, the channels selected will automatically be forced into Analog mode, regardless of the pin function previously defined. The only exception to this is the comparator, where the analog input to the comparator and the ADC will be active at the same time. It is the users responsibility to ensure that the ADC loading on the comparator input does not affect their application. The ANS<1:0> bits are active regardless of the condition of ADON. CHS<1:0> bits default to 11 after any Reset. If the ADON bit is clear, the GO/DONE bit cannot be set. C1OUT, when enabled, overrides AN2.
bit 5-4
bit 3-2
bit 1
bit 0
3: 4: 5: 6: Legend:
R = Readable bit -n = Value at POR
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
(c) 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 53
PIC12F510/16F506
REGISTER 9-2: ADRES REGISTER
R-X bit 7 Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R-X R-X R-X ADRES4 R-X ADRES3 R-X ADRES2 R-X ADRES1 R-X ADRES0 bit 0 ADRES7 ADRES6 ADRES5
EXAMPLE 9-1:
PERFORMING AN ANALOG-TO-DIGITAL CONVERSION
EXAMPLE 9-2:
CHANNEL SELECTION CHANGE DURING CONVERSION
;configure A/D
;Sample code operates out of BANK0
MOVLW 0xF1 ;configure A/D MOVWF ADCON0 BSF ADCON0, 1 ;start conversion BTFSC ADCON0, 1;wait for `DONE' GOTO loop0 MOVF ADRES, W ;read result MOVWF result0 ;save result BSF ADCON0, 2 ;setup for read of ;channel 1 BSF ADCON0, 1 ;start conversion BTFSC ADCON0, 1;wait for `DONE' GOTO loop1 MOVF ADRES, W ;read result MOVWF result1 ;save result BSF ADCON0, 3 ;setup for read of BCF ADCON0, 2 ;channel 2 BSF ADCON0, 1 ;start conversion BTFSC ADCON0, 1;wait for `DONE' GOTO loop2 MOVF ADRES, W ;read result MOVWF result2 ;save result
MOVLW 0xF1 MOVWF ADCON0 BSF ADCON0, 1 BSF ADCON0, 2 loop0
loop0
;start conversion ;setup for read of ;channel 1 BTFSC ADCON0, 1;wait for `DONE' GOTO loop0 MOVF ADRES, W ;read result MOVWF result0 ;save result BSF ADCON0, 1 ;start conversion BSF ADCON0, 3 ;setup for read of BCF ADCON0, 2 ;channel 2 BTFSC ADCON0, 1;wait for `DONE' GOTO loop1 MOVF ADRES, W ;read result MOVWF result1 ;save result BSF ADCON0, 1 ;start conversion BTFSC ADCON0, 1;wait for `DONE' GOTO loop2 MOVF ADRES, W ;read result MOVWF result2 ;save result CLRF ADCON0 ;optional: returns ;pins to Digital mode and turns off ;the ADC module
loop1
loop1
loop2
loop2
DS41268B-page 54
Preliminary
(c) 2006 Microchip Technology Inc.
PIC12F510/16F506
10.0 SPECIAL FEATURES OF THE CPU
10.1 Configuration Bits
The PIC12F510/16F506 Configuration Words consist of 12 bits. Configuration bits can be programmed to select various device configurations. Three bits are for the selection of the oscillator type; (two bits on the PIC12F510), one bit is the Watchdog Timer enable bit, one bit is the MCLR enable bit and one bit is for code protection (Register 10-1, Register 10-2).
What sets a microcontroller apart from other processors are special circuits that deal with the needs of realtime applications. The PIC12F510/16F506 microcontrollers have a host of such features intended to maximize system reliability, minimize cost through elimination of external components, provide powersaving operating modes and offer code protection. These features are: * Oscillator Selection * Reset: - Power-on Reset (POR) - Device Reset Timer (DRT) - Wake-up from Sleep on Pin Change * Watchdog Timer (WDT) * Sleep * Code Protection * ID Locations * In-Circuit Serial ProgrammingTM (ICSPTM) * Clock Out The PIC12F510/16F506 devices have a Watchdog Timer, which can be shut off only through Configuration bit WDTE. It runs off of its own RC oscillator for added reliability. If using HS (PIC16F506), XT or LP selectable oscillator options, there is always a delay, provided by the Device Reset Timer (DRT), intended to keep the chip in Reset until the crystal oscillator is stable. If using INTOSC, EXTRC or EC there is an 1.125 ms (nominal) delay only on VDD power-up. With this timer on-chip, most applications need no external Reset circuitry. The Sleep mode is designed to offer a very low-current Power-Down mode. The user can wake-up from Sleep through a change-on-input pin or through a Watchdog Timer time-out. Several oscillator options are also made available to allow the part to fit the application, including an internal 4/8 MHz oscillator. The EXTRC oscillator option saves system cost while the LP crystal option saves power. A set of Configuration bits are used to select various options.
(c) 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 55
PIC12F510/16F506
REGISTER 10-1:
-- bit 11 bit 11-6: Unimplemented: Read as `1' bit 5 IOSCFS: Internal Oscillator Frequency Select bit 1 = 8 MHz INTOSC speed 0 = 4 MHz INTOSC speed MCLRE: Master Clear Enable bit 1 = GP3/MCLR pin functions as MCLR 0 = GP3/MCLR pin functions as GP3, MCLR internally tied to VDD CP: Code Protection bit 1 = Code protection off 0 = Code protection on WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled FOSC1:FOSC0: Oscillator Selection bits 00 = LP oscillator with 18 ms DRT 01 = XT oscillator with 18 ms DRT 10 = INTOSC with 1.125 ms DRT(1), (2) 11 = EXTRC with 1.125 ms DRT(1), (2) Note 1: Refer to the "PIC12F510 Memory Programming Specification", DS41257 to determine how to access the Configuration Word. 2: It is the responsibility of the application designer to ensure the use of the 1.125 ms (nominal) DRT will result in acceptable operation. Refer to Electrical Specifications for VDD rise time and stability requirements for this mode of operation. Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = bit is set U = Unimplemented bit, read as `0' `0' = bit is cleared x = bit is unknown --
CONFIGURATION WORD - PIC12F510
-- -- -- -- IOSCFS MCLRE CP WDTE FOSC1 FOSC0 bit 0
bit 4:
bit 3:
bit 2:
bit 1-0:
DS41268B-page 56
Preliminary
(c) 2006 Microchip Technology Inc.
PIC12F510/16F506
REGISTER 10-2:
-- bit 11 bit 11-7: Unimplemented: Read as `1' bit 6: IOSCFS: Internal Oscillator Frequency Select bit 1 = 8 MHz INTOSC speed 0 = 4 MHz INTOSC speed MCLRE: Master Clear Enable bit 1 = RB3/MCLR pin functions as MCLR 0 = RB3/MCLR pin functions as RB3, MCLR tied internally to VDD CP: Code Protection bit 1 = Code protection off 0 = Code protection on WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled FOSC2:FOSC0: Oscillator Selection bits 000 = LP oscillator and 18 ms DRT 001 = XT oscillator and 18 ms DRT 010 = HS oscillator and 18 ms DRT 011 = EC oscillator with RB4 function on RB4/OSC2/CLKOUT and 1.125 ms DRT(1), (2) 100 = INTOSC with RB4 function on RB4/OSC2/CLKOUT and 1.125 ms DRT(1), (2) 101 = INTOSC with CLKOUT function on RB4/OSC2/CLKOUT and 1.125 ms DRT(1), (2) 110 = EXTRC with RB4 function on RB4/OSC2/CLKOUT and 1.125 ms DRT(1), (2) 111 = EXTRC with CLKOUT function on RB4/OSC2/CLKOUT and 1.125 ms DRT(1), (2) Note 1: Refer to the "PIC16F506 Memory Programming Specification", DS41258, to determine how to access the Configuration Word. 2: It is the responsibility of the application designer to ensure the use of the 1.125 ms (nominal) DRT will result in acceptable operation. Refer to Electrical Specifications for VDD rise time and stability requirements for this mode of operation. Legend: R = Readable bit -n = bLANK W = Writable bit `1' = bit is set U = Unimplemented bit, read as `0' `0' = bit is cleared x = bit is unknown --
CONFIGURATION WORD - PIC16F506
-- -- -- IOSCFS MCLRE CP WDTE FOSC2 FOSC1 FOSC0 bit 0
bit 5:
bit 4:
bit 3:
bit 2-0:
(c) 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 57
PIC12F510/16F506
10.2
10.2.1
Oscillator Configurations
OSCILLATOR TYPES
FIGURE 10-1:
The PIC12F510/16F506 devices can be operated in up to six different oscillator modes. The user can program up to three Configuration bits (FOSC<1:0> [PIC12F510], FOSC<2:0> [PIC16F506]). To select one of these modes: *LP: *XT: *HS: Low-Power Crystal Crystal/Resonator High-Speed Crystal/Resonator (PIC16F506 only) *INTOSC: Internal 4/8 MHz Oscillator *EXTRC: External Resistor/Capacitor *EC: External High-Speed Clock Input (PIC16F506 only)
CRYSTAL OPERATION (OR CERAMIC RESONATOR) (HS, XT OR LP OSC CONFIGURATION)
OSC1 PIC12F510 PIC16F506 Sleep RF(3) OSC2
C1(1)
XTAL RS(2) C2(1) Note 1: 2: 3:
To internal logic
10.2.2
CRYSTAL OSCILLATOR/CERAMIC RESONATORS
See Capacitor Selection tables for recommended values of C1 and C2. A series resistor (RS) may be required for AT strip cut crystals. RF approx. value = 10 M.
In HS (PIC16F506), XT or LP modes, a crystal or ceramic resonator is connected to the (GP5/RB5)/ OSC1/(CLKIN) and (GP4/RB4)/OSC2/(CLKOUT) pins to establish oscillation (Figure 10-1). The PIC12F510/ 16F506 oscillator designs require the use of a parallel cut crystal. Use of a series cut crystal may give a frequency out of the crystal manufacturers specifications. When in HS (PIC16F506), XT or LP modes, the device can have an external clock source drive the (GP5/ RB5)/OSC1/CLKIN pin (Figure 10-2). Note 1: This device has been designed to perform to the parameters of its data sheet. It has been tested to an electrical specification designed to determine its conformance with these parameters. Due to process differences in the manufacture of this device, this device may have different performance characteristics than its earlier version. These differences may cause this device to perform differently in your application than the earlier version of this device. 2: The user should verify that the device oscillator starts and performs as expected. Adjusting the loading capacitor values and/or the Oscillator mode may be required.
FIGURE 10-2:
EXTERNAL CLOCK INPUT OPERATION (HS, XT OR LP OSC CONFIGURATION)
OSC1
Clock from ext. system Open
PIC12F510 PIC16F506
OSC2
TABLE 10-1:
CAPACITOR SELECTION FOR CERAMIC RESONATORS - PIC12F510/16F506(1)
Cap. Range C1 30 pF 10-47 pF Cap. Range C2 30 pF 10-47 pF
Osc. Type XT HS(2) Note 1:
Resonator Freq. 4.0 MHz 16 MHz
2:
These values are for design guidance only. Since each resonator has its own characteristics, the user should consult the resonator manufacturer for appropriate values of external components. PIC16F506 only.
DS41268B-page 58
Preliminary
(c) 2006 Microchip Technology Inc.
PIC12F510/16F506
TABLE 10-2: CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR - PIC12F510/16F506(2)
Cap.Range C1 15 pF 47-68 pF 15 pF 15 pF 15-47 pF Cap. Range C2 15 pF 47-68 pF 15 pF 15 pF 15-47 pF
XTAL 10k 20 pF 20 pF
FIGURE 10-3:
EXTERNAL PARALLEL RESONANT CRYSTAL OSCILLATOR CIRCUIT
To Other Devices
Osc. Type LP XT
Resonator Freq. 32 kHz(1) 200 kHz 1 MHz 4 MHz 20 MHz
+5V 10k 4.7k 74AS04 74AS04 CLKIN PIC12F510 PIC16F506 10k
HS(3) Note 1: 2:
3:
For VDD > 4.5V, C1 = C2 30 pF is recommended. These values are for design guidance only. Rs may be required to avoid overdriving crystals beyond the drive level specification. Since each crystal has its own characteristics, the user should consult the crystal manufacturer for appropriate values of external components. PIC16F506 only.
10.2.3
EXTERNAL CRYSTAL OSCILLATOR CIRCUIT
Figure 10-4 shows a series resonant oscillator circuit. This circuit is also designed to use the fundamental frequency of the crystal. The inverter performs a 180degree phase shift in a series resonant oscillator circuit. The 330 resistors provide the negative feedback to bias the inverters in their linear region.
FIGURE 10-4:
Either a prepackaged oscillator or a simple oscillator circuit with TTL gates can be used as an external crystal oscillator circuit. Prepackaged oscillators provide a wide operating range and better stability. A well-designed crystal oscillator will provide good performance with TTL gates. Two types of crystal oscillator circuits can be used: one with parallel resonance or one with series resonance. Figure 10-3 shows implementation of a parallel resonant oscillator circuit. The circuit is designed to use the fundamental frequency of the crystal. The 74AS04 inverter performs the 180-degree phase shift that a parallel oscillator requires. The 4.7 k resistor provides the negative feedback for stability. The 10 k potentiometers bias the 74AS04 in the linear region. This circuit could be used for external oscillator designs.
EXTERNAL SERIES RESONANT CRYSTAL OSCILLATOR CIRCUIT
330 74AS04 74AS04 CLKIN To Other Devices
330 74AS04 0.1 mF XTAL
PIC12F510 PIC16F506
10.2.4
EXTERNAL RC OSCILLATOR
For timing insensitive applications, the EXTRC device option offers additional cost savings. The EXTRC oscillator frequency is a function of the supply voltage, the resistor (REXT) and capacitor (CEXT) values, and the operating temperature. In addition to this, the oscillator frequency will vary from unit-to-unit due to normal process parameter variation. Furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low CEXT values. The user also needs to take into account variation due to tolerance of external R and C components used. Figure 10-5 shows how the R/C combination is connected to the PIC12F510/16F506 devices. For REXT values below 5.0 k, the oscillator operation may become unstable or stop completely. For very high REXT values (e.g., 1 M), the oscillator becomes sensitive to noise, humidity and leakage. Thus, we recommend keeping REXT between 5.0 k and 100 k.
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Preliminary
DS41268B-page 59
PIC12F510/16F506
Although the oscillator will operate with no external capacitor (CEXT = 0 pF), we recommend using values above 20 pF for noise and stability reasons. With no capacitance or small external capacitance, the oscillation frequency can vary dramatically due to changes in external capacitances, such as PCB trace capacitance or package lead frame capacitance. Section 13.0 "Electrical Characteristics", shows RC frequency variation from part-to-part due to normal process variation. The variation is larger for larger values of R (since leakage current variation will affect RC frequency more for large R) and for smaller values of C (since variation of input capacitance will affect RC frequency more). Also, see the Electrical Specifications section for variation of oscillator frequency due to VDD for given REXT/CEXT values, as well as frequency variation due to operating temperature for given R, C and VDD values.
FIGURE 10-6:
EXTERNAL CLOCK INPUT OPERATION
PIC16F506: EC, HS, XT, LP
Clock From ext. system RB5/OSC1/CLKIN
OSC2/CLKOUT/RB4
OSC2/CLKOUT/RB4(1)
PIC12F510: XT, LP
Clock From ext. system GP5/OSC1/CLKIN
OSC2 Note 1:
GP4/OSC2
RB4 is available in EC mode only.
FIGURE 10-5:
VDD REXT
EXTERNAL RC OSCILLATOR MODE
OSC1
Internal clock
CEXT VSS FOSC/4
N PIC12F510 PIC16F506 OSC2/CLKOUT
In addition, a calibration instruction is programmed into the last address of memory, which contains the calibration value for the internal RC oscillator. This location is always uncode protected, regardless of the code-protect settings. This value is programmed as a MOVLW XX instruction where XX is the calibration value, and is placed at the Reset vector. This will load the W register with the calibration value upon Reset and the PC will then roll over to the users program at address 0x000. The user then has the option of writing the value to the OSCCAL Register (05h) or ignoring it. OSCCAL, when written to with the calibration value, will "trim" the internal oscillator to remove process variation from the oscillator frequency. Note: Erasing the device will also erase the preprogrammed internal calibration value for the internal oscillator. The calibration value must be read prior to erasing the part so it can be reprogrammed correctly later.
10.2.5
INTERNAL 4/8 MHz RC OSCILLATOR
The internal RC oscillator provides a fixed 4/8 MHz (nominal) system clock (see Section 13.0 "Electrical Characteristics" for information on variation over voltage and temperature).
10.2.6
EXTERNAL CLOCK IN
For applications where a clock is already available elsewhere, users may directly drive the PIC12F510/ 16F506 devices provided that this external clock source meets the AC/DC timing requirements listed in Section 10.6 "Watchdog Timer (WDT)". Figure 10-6 below shows how an external clock circuit should be configured.
For the PIC12F510/16F506 devices, only bits <7:1> of OSCCAL are implemented. Bits CAL6-CAL0 are used for calibration. Adjusting CAL6-CAL0 from `0000000' to `1111111' changes the clock speed. See Register 4-3 for more information. Note: The 0 bit of OSCCAL is unimplemented and should be written as `0' when modifying OSCCAL for compatibility with future devices.
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PIC12F510/16F506
10.3 Reset
The device differentiates between various kinds of Reset: * * * * * * * Power-on Reset (POR) MCLR Reset during normal operation MCLR Reset during Sleep WDT Time-out Reset during normal operation WDT Time-out Reset during Sleep Wake-up from Sleep Reset on pin change Wake-up from Sleep Reset on comparator change
Some registers are not reset in any way, they are unknown on POR and unchanged in any other Reset. Most other registers are reset to "Reset state" on Power-on Reset (POR), MCLR, WDT or Wake-up from Sleep Reset on pin change or wake-up from Sleep Reset on comparator change. The exceptions are TO, PD, CWUF and RBWUF/GPWUF bits. They are set or cleared differently in different Reset situations. These bits are used in software to determine the nature of Reset. See Table 10-4 for a full description of Reset states of all registers.
TABLE 10-3:
Register W INDF TMR0 PCL STATUS FSR OSCCAL GPIO CM1CON0 ADCON0 ADRES OPTION TRISIO
RESET CONDITIONS FOR REGISTERS - PIC12F510
Address -- 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h -- -- Power-on Reset qqqq qqqu(1) xxxx xxxx xxxx xxxx 1111 1111 0001 1xxx 110x xxxx 1111 111--xx xxxx 1111 1111 1111 1100 xxxx xxxx 1111 1111 --11 1111 MCLR Reset, WDT Time-out, Wake-up On Pin Change, Wake-up on Comparator Change qqqq qqqu(1) uuuu uuuu uuuu uuuu 1111 1111 qq0q quuu(2) 11uu uuuu uuuu uuu--uu uuuu uuuu uuuu uu11 1100 uuuu uuuu 1111 1111 --11 1111
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as `0', q = value depends on condition. Note 1: Bits <7:2> of W register contain oscillator calibration values due to MOVLW XX instruction at top of memory. 2: See Table 10-5 for Reset value for specific conditions.
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Preliminary
DS41268B-page 61
PIC12F510/16F506
TABLE 10-4:
Register W INDF TMR0 PCL STATUS FSR OSCCAL PORTB PORTC CM1CON0 ADCON0 ADRES CM2CON0 VRCON OPTION TRISB TRISC
RESET CONDITIONS FOR REGISTERS - PIC16F506
Address -- 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch -- -- -- Power-on Reset qqqq qqqu(1) xxxx xxxx xxxx xxxx 1111 1111 0001 1xxx 110x xxxx 1111 111--xx xxxx --xx xxxx 1111 1111 1111 1100 xxxx xxxx 1111 1111 001- 1111 1111 1111 --11 1111 --11 1111 1111 1111 --11 1111 --11 1111 MCLR Reset, WDT Time-out, Wake-up On Pin Change, Wake-up on Comparator Change qqqq qqqu(1) uuuu uuuu uuuu uuuu 1111 1111 qq0q quuu(2) 11uu uuuu uuuu uuu--uu uuuu --uu uuuu uuuu uuuu uu11 1100 uuuu uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as `0', q = value depends on condition. Note 1: Bits <7:2> of W register contain oscillator calibration values due to MOVLW XX instruction at top of memory. 2: See Table 10-5 for Reset value for specific conditions.
TABLE 10-5:
Power-on Reset
RESET CONDITION FOR SPECIAL REGISTERS
STATUS Addr: 03h 0001 1xxx 000u uuuu 0001 0uuu 0000 0uuu 0000 uuuu 1001 0uuu 0101 0uuu PCL Addr: 02h 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111
MCLR Reset during normal operation MCLR Reset during Sleep WDT Reset during Sleep WDT Reset normal operation Wake-up from Sleep Reset on pin change Wake from Sleep Reset on Comparator Change
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as `0'.
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PIC12F510/16F506
10.3.1 MCLR ENABLE
This Configuration bit, when unprogrammed (left in the `1' state), enables the external MCLR function. When programmed, the MCLR function is tied to the internal VDD and the pin is assigned to be a I/O. See Figure 10-7. A simplified block diagram of the on-chip Power-on Reset circuit is shown in Figure 10-8. The Power-on Reset circuit and the Device Reset Timer (see Section 10.5 "Device Reset Timer (DRT)") circuit are closely related. On power-up, the Reset latch is set and the DRT is reset. The DRT timer begins counting once it detects MCLR, internal or external, to be high. After the time-out period, it will reset the Reset latch and thus end the on-chip Reset signal. A power-up example where MCLR is held low is shown in Figure 10-9. VDD is allowed to rise and stabilize before bringing MCLR high. The chip will actually come out of Reset TDRT msec after MCLR goes high. In Figure 10-10, the on-chip Power-on Reset feature is being used (MCLR and VDD are tied together or the pin is programmed to be (GP3/RB3). The VDD is stable before the Start-up timer times out and there is no problem in getting a proper Reset. However, Figure 10-11 depicts a problem situation where VDD rises too slowly. The time between when the DRT senses that MCLR is high and when MCLR and VDD actually reach their full value, is too long. In this situation, when the start-up timer times out, VDD has not reached the VDD (min) value and the chip may not function correctly. For such situations, we recommend that external RC circuits be used to achieve longer POR delay times (Figure 10-10). Note: When the devices start normal operation (exit the Reset condition), device operating parameters (voltage, frequency, temperature, etc.) must be met to ensure operation. If these conditions are not met, the device must be held in Reset until the operating conditions are met.
FIGURE 10-7:
GPWU/RBWU
MCLR SELECT
(GP3/RB3)/MCLR/VPP
MCLRE
Internal MCLR
10.4
Power-on Reset (POR)
The PIC12F510/16F506 devices incorporate an onchip Power-on Reset (POR) circuitry, which provides an internal chip Reset for most power-up situations. The on-chip POR circuit holds the chip in Reset until VDD has reached a high enough level for proper operation. The POR is active regardless of the state of the MCLR enable bit. An internal weak pull-up resistor is implemented using a transistor (refer to Table 13-4 for the pull-up resistor ranges). This will eliminate external RC components usually needed to create an external Power-on Reset. A maximum rise time for VDD is specified. See Section 13.0 "Electrical Characteristics" for details. When the devices start normal operation (exit the Reset condition), device operating parameters (voltage, frequency, temperature,...) must be met to ensure operation. If these conditions are not met, the devices must be held in Reset until the operating parameters are met.
For additional information, refer to Application Notes AN522, "Power-Up Considerations" (DS00522) and AN607, "Power-up Trouble Shooting" (DS00607).
(c) 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 63
PIC12F510/16F506
FIGURE 10-8:
VDD Power-up Detect (GP3/RB3)/MCLR/VPP MCLR Reset S MCLRE R WDT Time-out Pin Change Sleep Comparator Change Wake-up on Comparator Change WDT Reset Start-up Timer (10 ms, 1.125 ms or 18 ms) Q CHIP Reset Q POR (Power-on Reset)
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
Wake-up on pin Change Reset
FIGURE 10-9:
TIME-OUT SEQUENCE ON POWER-UP (MCLR PULLED LOW)
VDD MCLR Internal POR TDRT
DRT Time-out Internal Reset
FIGURE 10-10:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): FAST VDD RISE TIME
VDD MCLR Internal POR TDRT
DRT Time-out
Internal Reset
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Preliminary
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PIC12F510/16F506
FIGURE 10-11: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): SLOW VDD RISE TIME
V1 VDD MCLR Internal POR TDRT
DRT Time-out
Internal Reset Note: When VDD rises slowly, the TDRT time-out expires long before VDD has reached its final value. In this example, the chip will reset properly if, and only if, V1 VDD min.
(c) 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 65
PIC12F510/16F506
10.5 Device Reset Timer (DRT)
TABLE 10-6:
Oscillator Configuration LP XT HS(1) EC(1) INTOSC EXTRC Note 1: Note:
TYPICAL DRT PERIODS
POR Reset 18 ms 18 ms 18 ms 1.125 ms 1.125 ms 1.125 ms Subsequent Resets 18 ms 18 ms 18 ms 10 s 10 s 10 s
On the PIC12F510/16F506 devices, the DRT runs any time the device is powered up. DRT runs from Reset and varies based on oscillator selection and Reset type (see Table 10-6). The DRT operates from a free running on-chip oscillator that is separate from INTOSC. The processor is kept in Reset as long as the DRT is active. The DRT delay allows VDD to rise above VDD minimum and for the oscillator to stabilize. Oscillator circuits, based on crystals or ceramic resonators, require a certain time after power-up to establish a stable oscillation. The on-chip DRT keeps the devices in a Reset for a set period, as stated in Table 10-6, after MCLR has reached a logic high (VIH MCLR) level. Programming (GP3/RB3)/MCLR/VPP as MCLR and using an external RC network connected to the MCLR input is not required in most cases. This allows savings in cost-sensitive and/or space restricted applications, as well as allowing the use of the (GP3/RB3)/MCLR/ VPP pin as a general purpose input. The DRT delays will vary from chip-to-chip due to VDD, temperature and process variation. See AC parameters for details. The DRT will also be triggered upon a Watchdog Timer time-out from Sleep. This is particularly important for applications using the WDT to wake from Sleep mode automatically. Reset sources are POR, MCLR, WDT time-out, Wakeup on Pin Change and Wake-up on Comparator Change. See Section 10.9.2 "Wake-up from Sleep Reset", Notes 1, 2 and 3.
PIC16F506 only It is the responsibility of the application designer to ensure the use of the 1.125 ms nominal DRT will result in acceptable operation. Refer to Electrical Specifications for VDD rise time and stability requirements for this mode of operation.
10.6.1
WDT PERIOD
The WDT has a nominal time-out period of 18 ms (with no prescaler). If a longer time-out period is desired, a prescaler with a divisor ratio of up to 1:128 can be assigned to the WDT (under software control) by writing to the OPTION register. Thus, a time-out period of a nominal 2.3 seconds can be realized. These periods vary with temperature, VDD and part-to-part process variations (see DC specs). Under worst case conditions (VDD = Min., Temperature = Max., max. WDT prescaler), it may take several seconds before a WDT time-out occurs.
10.6
Watchdog Timer (WDT)
The Watchdog Timer (WDT) is a free running on-chip RC oscillator that does not require any external components. This RC oscillator is separate from the external RC oscillator of the (GP5/RB5)/OSC1/CLKIN pin and the internal 4/8 MHz oscillator. This means that the WDT will run even if the main processor clock has been stopped, for example, by execution of a SLEEP instruction. During normal operation or Sleep, a WDT Reset or wake-up Reset generates a device Reset. The TO bit (STATUS<4>) will be cleared upon a Watchdog Timer Reset. The WDT can be permanently disabled by programming the configuration WDTE as a `0' (see Section 10.1 "Configuration Bits"). Refer to the PIC12F510/16F506 Programming Specifications to determine how to access the Configuration Word.
10.6.2
WDT PROGRAMMING CONSIDERATIONS
The CLRWDT instruction clears the WDT and the postscaler, if assigned to the WDT, and prevents it from timing out and generating a device Reset. The SLEEP instruction resets the WDT and the postscaler, if assigned to the WDT. This gives the maximum Sleep time before a WDT wake-up Reset.
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Preliminary
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PIC12F510/16F506
FIGURE 10-12: WATCHDOG TIMER BLOCK DIAGRAM
From Timer0 Clock Source (Figure 6-5) 0 Watchdog Timer 1 M U X Postscaler
8-to-1 MUX WDTE PSA
PS<2:0>
To Timer0 (Figure 6-4) 0 MUX 1 PSA
WDT Time-out
Note 1:
T0CS, T0SE, PSA, PS<2:0> are bits in the OPTION register.
TABLE 10-7:
Address N/A N/A
SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER
Name Bit 7 Bit 6 GPPU RBPU Bit 5 T0CS T0CS Bit 4 T0SE T0SE Bit 3 PSA PSA Bit 2 PS2 PS2 Bit 1 Bit 0 PS1 PS1 PS0 PS0 Value on Power-On Reset 1111 1111 1111 1111 Value on All Other Resets 1111 1111 1111 1111
OPTION(1) GPWU OPTION(2) RBWU
Legend: Shaded boxes = Not used by Watchdog Timer. - = unimplemented, read as `0', u = unchanged. Note 1: PIC12F510 only. 2: PIC16F506 only.
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Preliminary
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PIC12F510/16F506
10.7 Time-out Sequence, Power-down and Wake-up from Sleep Status Bits (TO, PD, GPWUF/RBWUF)
FIGURE 10-14:
VDD VDD R1 Q1 R2 MCLR(2) PIC12F510 PIC16F506
BROWN-OUT PROTECTION CIRCUIT 2
The TO, PD and (GPWUF/RBWUF) bits in the STATUS register can be tested to determine if a Reset condition has been caused by a power-up condition, a MCLR or Watchdog Timer (WDT) Reset.
TABLE 10-8:
TO/PD/(GPWUF/RBWUF) STATUS AFTER RESET
PD 0 u 0 1 u 0 0 Reset Caused By WDT wake-up from Sleep WDT time-out (not from Sleep) MCLR wake-up from Sleep Power-up MCLR not during Sleep Wake-up from Sleep on pin change Wake-up from Sleep on comparator change
2: Note 1:
40k(1)
CWUF 0 0 0 0 0 0 1
GPWUF/ TO RBWUF 0 0 0 0 0 1 0 0 0 1 1 u 1 1
This brown-out circuit is less expensive, although less accurate. Transistor Q1 turns off when VDD is below a certain level such that: R1 VDD * R1 + R2 = 0.7V
Pin must be configured as MCLR.
FIGURE 10-15:
VDD MCP809 VSS RST
BROWN-OUT PROTECTION CIRCUIT 3
Bypass Capacitor VDD
VDD
Legend: u = unchanged
MCLR PIC12F510 PIC16F506
10.8
Reset on Brown-out
A brown-out is a condition where device power (VDD) dips below its minimum value, but not to zero, and then recovers. The device should be reset in the event of a brown-out. To reset PIC12F510/16F506 devices when a brownout occurs, external brown-out protection circuits may be built, as shown in Figure 10-13 and Figure 10-14.
Note:
This brown-out protection circuit employs Microchip Technology's MCP809 microcontroller supervisor. There are 7 different trip point selections to accommodate 5V to 3V systems.
FIGURE 10-13:
VDD
BROWN-OUT PROTECTION CIRCUIT 1
VDD
33k 10k Q1 MCLR(2)
PIC12F510 PIC16F506
40k(1)
Note 1: 2:
This circuit will activate Reset when VDD goes below Vz + 0.7V (where Vz = Zener voltage). Pin must be configured as MCLR.
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PIC12F510/16F506
10.9 Power-Down Mode (Sleep)
Note 1: Caution: Right before entering Sleep, read the comparator Configuration register(s) CM1CON0 and CM2CON0. When in Sleep, wake-up occurs when the comparator output bit C1OUT and C2OUT change from the state they were in at the last reading. If a wake-up on comparator change occurs and the pins are not read before re-entering Sleep, a wake-up will occur immediately, even if no pins change while in Sleep mode. 2: For 16F506 only. The WDT is cleared when the device wakes from Sleep, regardless of the wake-up source. A device may be powered down (Sleep) and later powered up (wake-up from Sleep Reset).
10.9.1
SLEEP
The Power-Down mode is entered by executing a SLEEP instruction. If enabled, the Watchdog Timer will be cleared but keeps running, the TO bit (STATUS<4>) is set, the PD bit (STATUS<3>) is cleared and the oscillator driver is turned off. The I/O ports maintain the status they had before the SLEEP instruction was executed (driving high, driving low or high-impedance). Note: A device Reset generated by a WDT time-will not drive the MCLR pin low.
For lowest current consumption while powered down, all input pins should be at VDD or VSS and (GP3/RB3)/ MCLR/VPP pin must be at a logic high level if MCLR is enabled.
10.10 Program Verification/Code Protection
If the code protection bit has not been programmed, the on-chip program memory can be read out for verification purposes. The first 64 locations and the last location (OSCCAL) can be read, regardless of the code protection bit setting. The last memory location can be read regardless of the code protection bit setting on the PIC12F510/16F506 devices.
10.9.2
WAKE-UP FROM SLEEP RESET
The device can wake-up from Sleep through one of the following events: 1. 2. 3. An external Reset input on (GP3/RB3)/MCLR/ VPP pin when configured as MCLR. A Watchdog Timer Time-out Reset (if WDT was enabled). A change-on-input pin GP0/RB0, GP1/RB1, GP3/RB3 or RB4 when wake-up on change is enabled. A change in the comparator ouput bits, C1OUT and C2OUT (if comparator wake-up is enabled).
10.11 ID Locations
Four memory locations are designated as ID locations where the user can store checksum or other code identification numbers. These locations are not accessible during normal execution, but are readable and writable during Program/Verify. Use only the lower 4 bits of the ID locations and always set the upper 4 bits as `1's. The upper 4 bits are unimplemented. These locations can be read regardless of the code protect setting.
4.
These events cause a device Reset. The TO, PD, CWUF and GPWUF/RBWUF bits can be used to determine the cause of device Reset. The TO bit is cleared if a WDT time-out occurred (and caused wake-up). The PD bit, which is set on power-up, is cleared when SLEEP is invoked. The CWUF bit indicates a change in comparator output state while the device was in Sleep. The GPWUF/RBWUF bit indicates a change in state while in Sleep at pins GP0/RB0, GP1/RB1, GP3/RB3 or RB4 (since the last file or bit operation on GP/RB port). Note: Caution: Right before entering Sleep, read the input pins. When in Sleep, wakeup occurs when the values at the pins change from the state they were in at the last reading. If a wake-up on change occurs and the pins are not read before reentering Sleep, a wake-up will occur immediately even if no pins change while in Sleep mode.
(c) 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 69
PIC12F510/16F506
10.12 In-Circuit Serial ProgrammingTM (ICSPTM)
The PIC12F510/16F506 microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data, and three other lines for power, ground and the programming voltage. This allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. This also allows the most recent firmware, or a custom firmware, to be programmed. The devices are placed into a Program/Verify mode by holding the GP1/RB1 and GP0/RB0 pins low while raising the MCLR (VPP) pin from VIL to VIHH (see programming specification). GP1/RB1 becomes the programming clock and GP0/RB0 becomes the programming data. Both GP1/RB1 and GP0/RB0 are Schmitt Trigger inputs in this mode. After Reset, a 6-bit command is supplied to the device. Depending on the command and if the command was a Load or a Read, 14 bits of program data are then supplied to or from the device. For complete details of serial programming, please refer to the PIC12F510/16F506 Programming Specifications. A typical In-Circuit Serial Programming connection is shown in Figure 10-16.
FIGURE 10-16:
TYPICAL IN-CIRCUIT SERIAL PROGRAMMING CONNECTION
To Normal Connections PIC12F510 PIC16F506 VDD VSS MCLR/VPP GP1/RB1 GP0/RB0 VDD To Normal Connections
External Connector Signals +5V 0V VPP CLK Data I/O
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PIC12F510/16F506
11.0 INSTRUCTION SET SUMMARY
The PIC16 instruction set is highly orthogonal and is comprised of three basic categories. * Byte-oriented operations * Bit-oriented operations * Literal and control operations Each PIC16 instruction is a 12-bit word divided into an opcode, which specifies the instruction type, and one or more operands which further specify the operation of the instruction. The formats for each of the categories is presented in Figure 11-1, while the various opcode fields are summarized in Table 11-1. For byte-oriented instructions, `f' represents a file register designator and `d' represents a destination designator. The file register designator specifies which file register is to be used by the instruction. The destination designator specifies where the result of the operation is to be placed. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed in the file register specified in the instruction. For bit-oriented instructions, `b' represents a bit field designator which selects the number of the bits affected by the operation, while `f' represents the number of the file in which the bit is located. For literal and control operations, `k' represents an 8 or 9-bit constant or literal value. All instructions are executed within a single instruction cycle, unless a conditional test is true or the program counter is changed as a result of an instruction. In this case, the execution takes two instruction cycles. One instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4 MHz, the normal instruction execution time is 1 s. If a conditional test is true or the program counter is changed as a result of an instruction, the instruction execution time is 2 s. Figure 11-1 shows the three general formats that the instructions can have. All examples in the figure use the following format to represent a hexadecimal number: 0xhhh where `h' signifies a hexadecimal digit.
FIGURE 11-1:
GENERAL FORMAT FOR INSTRUCTIONS
6 5 d 4 f (FILE #) 0
Byte-oriented file register operations 11 OPCODE
d = 0 for destination W d = 1 for destination f f = 5-bit file register address Bit-oriented file register operations 11 OPCODE 87 54 b (BIT #) 0 f (FILE #)
TABLE 11-1:
Field f W b k x
OPCODE FIELD DESCRIPTIONS
Description
b = 3-bit bit address f = 5-bit file register address Literal and control operations (except GOTO) 11 OPCODE k = 8-bit immediate value Literal and control operations - GOTO instruction 11 OPCODE k = 9-bit immediate value 9 8 k (literal) 0 8 7 k (literal) 0
Register file address (0x00 to 0x7F) Working register (accumulator) Bit address within an 8-bit file register Literal field, constant data or label Don't care location (= 0 or 1) The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. Destination select; d = 0 (store result in W) d = 1 (store result in file register `f') Default is d = 1 Label name Top-of-Stack Program Counter Watchdog Timer counter Time-out bit Power-down bit Destination, either the W register or the specified register file location Options Contents Assigned to Register bit field In the set of
d
label TOS PC WDT TO PD dest [ ( <> ] )
italics User defined term (font is courier)
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TABLE 11-2:
Mnemonic, Operands ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF f, d f, d f - f, d f, d f, d f, d f, d f, d f, d f - f, d f, d f, d f, d f, d
INSTRUCTION SET SUMMARY
12-Bit Opcode Description Cycles MSb LSb Status Notes Affected
0001 11df ffff C, DC, Z 1, 2, 4 Add W and f 1 0001 01df ffff AND W with f 1 Z 2, 4 0000 011f ffff Clear f 1 Z 4 0000 0100 0000 Clear W 1 Z 0010 01df ffff Complement f 1 Z 0000 11df ffff Decrement f 1 Z 2, 4 0010 11df ffff Decrement f, Skip if 0 1(2) None 2, 4 1 0010 10df ffff Increment f Z 2, 4 1(2) 0011 11df ffff Increment f, Skip if 0 None 2, 4 1 0001 00df ffff Inclusive OR W with f Z 2, 4 1 0010 00df ffff Move f Z 2, 4 1 0000 001f ffff Move W to f None 1, 4 1 0000 0000 0000 No Operation None 1 0011 01df ffff Rotate left f through Carry C 2, 4 1 0011 00df ffff Rotate right f through Carry C 2, 4 1 0000 10df ffff C, DC, Z 1, 2, 4 Subtract W from f 1 0011 10df ffff Swap f None 2, 4 1 0001 10df ffff Exclusive OR W with f Z 2, 4 BIT-ORIENTED FILE REGISTER OPERATIONS 0100 bbbf ffff None 2, 4 1 Bit Clear f BCF f, b 0101 bbbf ffff None 2, 4 1 Bit Set f BSF f, b 0110 bbbf ffff None Bit Test f, Skip if Clear 1(2) BTFSC f, b 1(2) 0111 bbbf ffff None f, b Bit Test f, Skip if Set BTFSS LITERAL AND CONTROL OPERATIONS ANDLW k AND literal with W 1 1110 kkkk kkkk Z CALL 1 k Call Subroutine 2 1001 kkkk kkkk None CLRWDT - Clear Watchdog Timer 1 0000 0000 0100 TO, PD None GOTO k Unconditional branch 2 101k kkkk kkkk Z IORLW k Inclusive OR literal with W 1 1101 kkkk kkkk None MOVLW k Move literal to W 1 1100 kkkk kkkk None OPTION - Load OPTION register 1 0000 0000 0010 None RETLW k Return, place literal in W 2 1000 kkkk kkkk SLEEP - Go into Standby mode 1 0000 0000 0011 TO, PD None 3 TRIS f Load TRIS register 1 0000 0000 0fff Z XORLW k Exclusive OR literal to W 1 1111 kkkk kkkk Note 1: The 9th bit of the Program Counter will be forced to a `0' by any instruction that writes to the PC except for GOTO. See Section 4.6 "Program Counter". 2: When an I/O register is modified as a function of itself (e.g. MOVF PORTB, 1), the value used will be that value present on the pins themselves. For example, if the data latch is `1' for a pin configured as input and is driven low by an external device, the data will be written back with a `0'. 3: The instruction TRIS f, where f = 6, causes the contents of the W register to be written to the tri-state latches of PORTB. A `1' forces the pin to a high-impedance state and disables the output buffers. 4: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared (if assigned to TMR0).
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ADDWF Syntax: Operands: Operation: Status Affected: Description: Add W and f [ label ] ADDWF 0 f 31 d [0,1] (W) + (f) (dest) C, DC, Z Add the contents of the W register and register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'. f,d BCF Syntax: Operands: Operation: Status Affected: Description: Bit Clear f [ label ] BCF 0 f 31 0b7 0 (f) None Bit `b' in register `f' is cleared. f,b
ANDLW Syntax: Operands: Operation: Status Affected: Description:
AND literal with W [ label ] ANDLW 0 k 255 (W).AND. (k) (W) Z The contents of the W register are AND'ed with the eight-bit literal `k'. The result is placed in the W register. k
BSF Syntax: Operands: Operation: Status Affected: Description:
Bit Set f [ label ] BSF 0 f 31 0b7 1 (f) None Bit `b' in register `f' is set. f,b
ANDWF Syntax: Operands: Operation: Description:
AND W with f [ label ] ANDWF 0 f 31 d [0,1] (W) .AND. (f) (dest) The contents of the W register are AND'ed with register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'. f,d
BTFSC Syntax: Operands: Operation: Status Affected: Description:
Bit Test f, Skip if Clear [ label ] BTFSC f,b 0 f 31 0b7 skip if (f) = 0 None If bit `b' in register `f' is `0', then the next instruction is skipped. If bit `b' is `0', then the next instruction fetched during the current instruction execution is discarded, and a NOP is executed instead, making this a two-cycle instruction.
Status Affected: Z
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BTFSS Syntax: Operands: Operation: Status Affected: Description: Bit Test f, Skip if Set [ label ] BTFSS f,b 0 f 31 0b<7 skip if (f) = 1 None If bit `b' in register `f' is `1', then the next instruction is skipped. If bit `b' is `1', then the next instruction fetched during the current instruction execution, is discarded and a NOP is executed instead, making this a two-cycle instruction. Status Affected: Description: CLRW Syntax: Operands: Operation: Clear W [ label ] CLRW None 00h (W); 1Z Z The W register is cleared. Zero bit (Z) is set.
CALL Syntax: Operands: Operation:
Subroutine Call [ label ] CALL k 0 k 255 (PC) + 1 Top-of-Stack; k PC<7:0>; (STATUS <6:5>) PC<10:9>; 0 PC<8> None Subroutine call. First, return address (PC + 1) is PUSHed onto the stack. The eight-bit immediate address is loaded into PC bits <7:0>. The upper bits PC<10:9> are loaded from STATUS <6:5>, PC<8> is cleared. CALL is a two-cycle instruction.
CLRWDT Syntax: Operands: Operation:
Clear Watchdog Timer [ label ] CLRWDT None 00h WDT; 0 WDT prescaler (if assigned); 1 TO; 1 PD TO, PD The CLRWDT instruction resets the WDT. It also resets the prescaler, if the prescaler is assigned to the WDT and not Timer0. Status bits TO and PD are set.
Status Affected: Description:
Status Affected: Description:
CLRF Syntax: Operands: Operation: Status Affected: Description:
Clear f [ label ] CLRF 0 f 31 00h (f); 1Z Z The contents of register `f' are cleared and the Z bit is set. f
COMF Syntax: Operands: Operation: Status Affected: Description:
Complement f [ label ] COMF 0 f 31 d [0,1] (f) (dest) Z The contents of register `f' are complemented. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'. f,d
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DECF Syntax: Operands: Operation: Status Affected: Description: Decrement f [ label ] DECF f,d 0 f 31 d [0,1] (f) - 1 (dest) Z Decrement register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'. INCF Syntax: Operands: Operation: Status Affected: Description: Increment f [ label ] 0 f 31 d [0,1] (f) + 1 (dest) Z The contents of register `f' are incremented. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'. INCF f,d
DECFSZ Syntax: Operands: Operation: Status Affected: Description:
Decrement f, Skip if 0 [ label ] DECFSZ f,d 0 f 31 d [0,1] (f) - 1 d; None The contents of register `f' are decremented. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'. If the result is `0', the next instruction, which is already fetched, is discarded and a NOP is executed instead making it a two-cycle instruction. skip if result = 0
INCFSZ Syntax: Operands: Operation: Status Affected: Description:
Increment f, Skip if 0 [ label ] 0 f 31 d [0,1] (f) + 1 (dest), skip if result = 0 None The contents of register `f' are incremented. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'. If the result is `0', then the next instruction, which is already fetched, is discarded and a NOP is executed instead making it a two-cycle instruction. INCFSZ f,d
GOTO Syntax: Operands: Operation: Status Affected: Description:
Unconditional Branch [ label ] GOTO k 0 k 511 k PC<8:0>; STATUS <6:5> PC<10:9> None GOTO is an unconditional branch. The 9-bit immediate value is loaded into PC bits <8:0>. The upper bits of PC are loaded from STATUS <6:5>. GOTO is a twocycle instruction.
IORLW Syntax: Operands: Operation: Status Affected: Description:
Inclusive OR literal with W [ label ] IORLW k 0 k 255 (W) .OR. (k) (W) Z The contents of the W register are OR'ed with the eight-bit literal `k'. The result is placed in the W register.
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IORWF Syntax: Operands: Operation: Status Affected: Description: Inclusive OR W with f [ label ] 0 f 31 d [0,1] (W).OR. (f) (dest) Z Inclusive OR the W register with register `f'. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'. IORWF f,d MOVWF Syntax: Operands: Operation: Status Affected: Description: Move W to f [ label ] 0 f 31 (W) (f) None Move data from the W register to register `f'. MOVWF f
MOVF Syntax: Operands: Operation: Status Affected: Description:
Move f [ label ] 0 f 31 d [0,1] (f) (dest) Z The contents of register `f' are moved to destination `d'. If `d' is `0', destination is the W register. If `d' is `1', the destination is file register `f'. `d' = 1 is useful as a test of a file register, since Status flag Z is affected. MOVF f,d
NOP Syntax: Operands: Operation: Status Affected: Description:
No Operation [ label ] None No operation None No operation. NOP
MOVLW Syntax: Operands: Operation: Status Affected: Description:
Move Literal to W [ label ] k (W) None The eight-bit literal `k' is loaded into the W register. The "don't cares" will be assembled as `0's. MOVLW k 0 k 255
OPTION Syntax: Operands: Operation: Status Affected: Description:
Load OPTION Register [ label ] None (W) Option None The content of the W register is loaded into the OPTION register. Option
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RETLW Syntax: Operands: Operation: Status Affected: Description: Return with Literal in W [ label ] RETLW k 0 k 255 k (W); TOS PC None The W register is loaded with the eight-bit literal `k'. The program counter is loaded from the top of the stack (the return address). This is a two-cycle instruction. Status Affected: Description: SLEEP Syntax: Operands: Operation: Enter SLEEP Mode [label ] None 00h WDT; 0 WDT prescaler; 1 TO; 0 PD TO, PD, RBWUF Time-out Status bit (TO) is set. The Power-down Status bit (PD) is cleared. RBWUF is unaffected. The WDT and its prescaler are cleared. The processor is put into Sleep mode with the oscillator stopped. See Section 10.9 "Power-Down Mode (Sleep)" on Sleep for more details. SLEEP
RLF Syntax: Operands: Operation: Status Affected: Description:
Rotate Left f through Carry [ label ] RLF 0 f 31 d [0,1] See description below C The contents of register `f' are rotated one bit to the left through the Carry flag. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is stored back in register `f'. C
register `f'
SUBWF Syntax: Operands: Operation: Status Affected: Description:
Subtract W from f [label ] SUBWF f,d
f,d
0 f 31 d [0,1] (f) - (W) (dest) C, DC, Z Subtract (2's complement method) the W register from register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'.
RRF Syntax: Operands: Operation: Status Affected: Description:
Rotate Right f through Carry [ label ] 0 f 31 d [0,1] See description below C The contents of register `f' are rotated one bit to the right through the Carry flag. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'. C
register `f'
SWAPF Syntax: Operands: Operation: Status Affected: Description:
Swap Nibbles in f [ label ] SWAPF f,d 0 f 31 d [0,1] (f<3:0>) (dest<7:4>); (f<7:4>) (dest<3:0>) None The upper and lower nibbles of register `f' are exchanged. If `d' is `0', the result is placed in W register. If `d' is `1', the result is placed in register `f'.
RRF f,d
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TRIS Syntax: Operands: Operation: Status Affected: Description: Load TRIS Register [ label ] TRIS f=6 (W) TRIS register f None TRIS register `f' (f = 6 or 7) is loaded with the contents of the W register Operation: Status Affected: Description: f XORWF Syntax: Operands: Exclusive OR W with f [ label ] XORWF 0 f 31 d [0,1] (W) .XOR. (f) (dest) Z Exclusive OR the contents of the W register with register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'. f,d
XORLW Syntax: Operands: Operation: Status Affected: Description:
Exclusive OR literal with W [label ] XORLW k 0 k 255 (W) .XOR. k (W) Z The contents of the W register are XOR'ed with the eight-bit literal `k'. The result is placed in the W register.
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12.0 DEVELOPMENT SUPPORT
12.1
The PICmicro(R) microcontrollers are supported with a full range of hardware and software development tools: * Integrated Development Environment - MPLAB(R) IDE Software * Assemblers/Compilers/Linkers - MPASMTM Assembler - MPLAB C18 and MPLAB C30 C Compilers - MPLINKTM Object Linker/ MPLIBTM Object Librarian - MPLAB ASM30 Assembler/Linker/Library * Simulators - MPLAB SIM Software Simulator * Emulators - MPLAB ICE 2000 In-Circuit Emulator - MPLAB ICE 4000 In-Circuit Emulator * In-Circuit Debugger - MPLAB ICD 2 * Device Programmers - PICSTART(R) Plus Development Programmer - MPLAB PM3 Device Programmer * Low-Cost Demonstration and Development Boards and Evaluation Kits
MPLAB Integrated Development Environment Software
The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit microcontroller market. The MPLAB IDE is a Windows(R) operating system-based application that contains: * A single graphical interface to all debugging tools - Simulator - Programmer (sold separately) - Emulator (sold separately) - In-Circuit Debugger (sold separately) * A full-featured editor with color-coded context * A multiple project manager * Customizable data windows with direct edit of contents * High-level source code debugging * Visual device initializer for easy register initialization * Mouse over variable inspection * Drag and drop variables from source to watch windows * Extensive on-line help * Integration of select third party tools, such as HI-TECH Software C Compilers and IAR C Compilers The MPLAB IDE allows you to: * Edit your source files (either assembly or C) * One touch assemble (or compile) and download to PICmicro MCU emulator and simulator tools (automatically updates all project information) * Debug using: - Source files (assembly or C) - Mixed assembly and C - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power.
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12.2 MPASM Assembler 12.5
The MPASM Assembler is a full-featured, universal macro assembler for all PICmicro MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel(R) standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging. The MPASM Assembler features include: * Integration into MPLAB IDE projects * User-defined macros to streamline assembly code * Conditional assembly for multi-purpose source files * Directives that allow complete control over the assembly process
MPLAB ASM30 Assembler, Linker and Librarian
MPLAB ASM30 Assembler produces relocatable machine code from symbolic assembly language for dsPIC30F devices. MPLAB C30 C Compiler uses the assembler to produce its object file. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. Notable features of the assembler include: * * * * * * Support for the entire dsPIC30F instruction set Support for fixed-point and floating-point data Command line interface Rich directive set Flexible macro language MPLAB IDE compatibility
12.6 12.3 MPLAB C18 and MPLAB C30 C Compilers
MPLAB SIM Software Simulator
The MPLAB C18 and MPLAB C30 Code Development Systems are complete ANSI C compilers for Microchip's PIC18 family of microcontrollers and dsPIC30F family of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use not found with other compilers. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger.
The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PICmicro MCUs and dsPIC(R) DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis. The trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on I/O, as well as internal registers. The MPLAB SIM Software Simulator fully supports symbolic debugging using the MPLAB C18 and MPLAB C30 C Compilers, and the MPASM and MPLAB ASM30 Assemblers. The software simulator offers the flexibility to develop and debug code outside of the laboratory environment, making it an excellent, economical software development tool.
12.4
MPLINK Object Linker/ MPLIB Object Librarian
The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler and the MPLAB C18 C Compiler. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: * Efficient linking of single libraries instead of many smaller files * Enhanced code maintainability by grouping related modules together * Flexible creation of libraries with easy module listing, replacement, deletion and extraction
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12.7 MPLAB ICE 2000 High-Performance In-Circuit Emulator 12.9 MPLAB ICD 2 In-Circuit Debugger
Microchip's In-Circuit Debugger, MPLAB ICD 2, is a powerful, low-cost, run-time development tool, connecting to the host PC via an RS-232 or high-speed USB interface. This tool is based on the Flash PICmicro MCUs and can be used to develop for these and other PICmicro MCUs and dsPIC DSCs. The MPLAB ICD 2 utilizes the in-circuit debugging capability built into the Flash devices. This feature, along with Microchip's In-Circuit Serial ProgrammingTM (ICSPTM) protocol, offers cost-effective, in-circuit Flash debugging from the graphical user interface of the MPLAB Integrated Development Environment. This enables a designer to develop and debug source code by setting breakpoints, single stepping and watching variables, and CPU status and peripheral registers. Running at full speed enables testing hardware and applications in real time. MPLAB ICD 2 also serves as a development programmer for selected PICmicro devices.
The MPLAB ICE 2000 In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PICmicro microcontrollers. Software control of the MPLAB ICE 2000 In-Circuit Emulator is advanced by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment. The MPLAB ICE 2000 is a full-featured emulator system with enhanced trace, trigger and data monitoring features. Interchangeable processor modules allow the system to be easily reconfigured for emulation of different processors. The architecture of the MPLAB ICE 2000 In-Circuit Emulator allows expansion to support new PICmicro microcontrollers. The MPLAB ICE 2000 In-Circuit Emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. The PC platform and Microsoft(R) Windows(R) 32-bit operating system were chosen to best make these features available in a simple, unified application.
12.10 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features a large LCD display (128 x 64) for menus and error messages and a modular, detachable socket assembly to support various package types. The ICSPTM cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PICmicro devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an SD/MMC card for file storage and secure data applications.
12.8
MPLAB ICE 4000 High-Performance In-Circuit Emulator
The MPLAB ICE 4000 In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for high-end PICmicro MCUs and dsPIC DSCs. Software control of the MPLAB ICE 4000 In-Circuit Emulator is provided by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment. The MPLAB ICE 4000 is a premium emulator system, providing the features of MPLAB ICE 2000, but with increased emulation memory and high-speed performance for dsPIC30F and PIC18XXXX devices. Its advanced emulator features include complex triggering and timing, and up to 2 Mb of emulation memory. The MPLAB ICE 4000 In-Circuit Emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. The PC platform and Microsoft Windows 32-bit operating system were chosen to best make these features available in a simple, unified application.
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12.11 PICSTART Plus Development Programmer
The PICSTART Plus Development Programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus Development Programmer supports most PICmicro devices in DIP packages up to 40 pins. Larger pin count devices, such as the PIC16C92X and PIC17C76X, may be supported with an adapter socket. The PICSTART Plus Development Programmer is CE compliant.
12.12 Demonstration, Development and Evaluation Boards
A wide variety of demonstration, development and evaluation boards for various PICmicro MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. The boards support a variety of features, including LEDs, temperature sensors, switches, speakers, RS-232 interfaces, LCD displays, potentiometers and additional EEPROM memory. The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEMTM and dsPICDEMTM demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ(R) security ICs, CAN, IrDA(R), PowerSmart(R) battery management, SEEVAL(R) evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Check the Microchip web page (www.microchip.com) and the latest "Product Selector Guide" (DS00148) for the complete list of demonstration, development and evaluation kits.
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13.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings Ambient temperature under bias.......................................................................................................... -40C to +125C Storage temperature ............................................................................................................................ -65C to +150C Voltage on VDD with respect to VSS ............................................................................................................... 0 to +7.0V Voltage on MCLR with respect to VSS.............................................................................................................0 to +14V Voltage on all other pins with respect to VSS ............................................................................... -0.3V to (VDD + 0.3V) Total power dissipation(1) .................................................................................................................................. 700 mW Max. current out of VSS pin ................................................................................................................................ 200 mA Max. current into VDD pin ................................................................................................................................... 150 mA Input clamp current, IIK (VI < 0 or VI > VDD)...................................................................................................................20 mA Output clamp current, IOK (VO < 0 or VO > VDD) ...........................................................................................................20 mA Max. output current sunk by any I/O pin .............................................................................................................. 25 mA Max. output current sourced by any I/O pin ......................................................................................................... 25 mA Max. output current sourced by I/O port ............................................................................................................ 100 mA Max. output current sunk by I/O port ................................................................................................................. 100 mA Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD - IOH} + {(VDD-VOH) x IOH} + (VOL x IOL)
NOTICE:
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
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FIGURE 13-1:
6.0 5.5 5.0 VDD (Volts) 4.5 4.0 3.5 3.0 2.5 2.0 0 4 8 10 20 25
VOLTAGE-FREQUENCY GRAPH, -40C TA +125C (PIC12F510)
Frequency (MHz)
FIGURE 13-2:
MAXIMUM OSCILLATOR FREQUENCY TABLE (PIC12F510)
LP
Oscillator Mode
XT EXTRC INTOSC 0 200 kHz 4 MHz 8 MHz 20 MHz
Frequency (MHz)
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FIGURE 13-3:
6.0 5.5 5.0 VDD (Volts) 4.5 4.0 3.5 3.0 2.5 2.0 0 4 8 10 20 25
VOLTAGE FREQUENCY GRAPH, -40C TA +125C (PIC16F506)
Frequency (MHz)
FIGURE 13-4:
MAXIMUM OSCILLATOR FREQUENCY TABLE (PIC16F506)
LP Oscillator Mode XT EXTRC INTOSC EC HS 0 200 kHz 4 MHz 8 MHz 20 MHz
Frequency (MHz)
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13.1 DC Characteristics: PIC12F510/16F506 (Industrial)
Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +85C (Industrial) Min 2.0 -- -- Typ(1) -- 1.5* Vss -- Max Units 5.5 -- -- -- V V V Conditions See Figure 13-1 Device in Sleep mode See Section 10.4 "Power-on Reset (POR)" DC CHARACTERISTICS Parm No. D001 D002 D003 D004 D010 Sym VDD VDR VPOR SVDD IDD Characteristic Supply Voltage RAM Data Retention Voltage(2) VDD Start Voltage to ensure Power-on Reset
VDD Rise Rate to ensure 0.05* Power-on Reset Supply Current(3) -- -- -- --
V/ms See Section 10.4 "Power-on Reset (POR)" for details A mA mA A A A A A A A FOSC = 4 MHz, VDD = 2.0V(4) FOSC = 8 MHz, VDD = 3.0V FOSC = 20 MHz, VDD = 5.0V FOSC = 32 kHz, VDD = 2.0V, WDT disabled VDD = 2.0V VDD = 2.0V VDD = 2.0V VDD = 2.0V VDD = 2.0V VDD = 2.0V
170 0.4 1.7 15 0.1 1.0 15 100 80 58
TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
D020 D022 D023 D024 D025 D026
IPD IWDT ICMP IADC
Power-Down Current(5) WDT Current(5) Comparator Current ADC Current
-- -- -- -- -- --
IVREF Internal Reference Current CVREF Comparator Voltage Reference Current
Legend: TBD = To be determined. * These parameters are characterized but not tested. Note 1: Data in the Typical ("Typ") column is based on characterization results at 25C. This data is for design guidance only and is not tested. 2: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data. 3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current consumption. a) The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified. b) For standby current measurements, the conditions are the same, except that the device is in Sleep mode. 4: Does not include current through REXT (in EXTRC mode only). The current through the resistor can be estimated by the formula: I = VDD/2REXT (mA) with REXT in k. 5: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS.
DS41268B-page 86
Preliminary
(c) 2006 Microchip Technology Inc.
PIC12F510/16F506
13.2 DC Characteristics: PIC12F510/16F506 (Extended)
Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +125C (Extended) Min 2.0 -- -- Typ(1) Max Units -- 1.5* Vss -- 5.5 -- -- -- V V V Conditions See Figure 13-1 Device in Sleep mode See Section 10.4 "Power-on Reset (POR)" DC CHARACTERISTICS Parm No. D001 D002 D003 D004 D010 Sym VDD VDR VPOR SVDD IDD Characteristic Supply Voltage RAM Data Retention Voltage(2) VDD Start Voltage to ensure Power-on Reset
VDD Rise Rate to ensure 0.05* Power-on Reset Supply Current(3) -- -- -- -- --
V/ms See Section 10.4 "Power-on Reset (POR)" for details A A mA mA A A A A A A A FOSC = 4 MHz, VDD = 5.0V FOSC = 4 MHz, VDD = 2.0V(4) FOSC = 8 MHz, VDD = 3.0V FOSC = 20 MHz, VDD = 5.0V FOSC = 32 kHz, VDD = 2.0V, WDT disabled VDD = 2.0V VDD = 2.0V VDD = 2.0V VDD = 2.0V VDD = 2.0V VDD = 2.0V
385 170 0.4 1.7 15 0.1 1.0 15 100 80 58
TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
D020 D022 D023 D024 D025 D026
IPD IWDT ICMP IADC
Power-Down Current(5) WDT Current(5) Comparator Current ADC Current
-- -- -- -- -- --
IVREF Internal Reference Current CVREF Comparator Voltage Reference Current
Legend: TBD = To be determined. * These parameters are characterized but not tested. Note 1: Data in the Typical ("Typ") column is based on characterization results at 25C. This data is for design guidance only and is not tested. 2: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data. 3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current consumption. a) The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified. b) For standby current measurements, the conditions are the same, except that the device is in Sleep mode. 4: Does not include current through REXT (in EXTRC mode only). The current through the resistor can be estimated by the formula: I = VDD/2REXT (mA) with REXT in k. 5: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS.
(c) 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 87
PIC12F510/16F506
13.3 DC Characteristics: PIC12F510/16F506 (Industrial, Extended)
Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +85C (industrial) -40C TA +125C (extended) Characteristic Input Low Voltage I/O ports D030 D030A D031 D032 D033 D033 D033 VIH with Schmitt Trigger buffer MCLR, T0CKI OSC1 (in EXTRC), EC(1) OSC1 (in HS) OSC1 (in XT and LP) Input High Voltage I/O ports D040 D040A with TTL buffer 2.0 0.25 VDD + 0.8V D041 D042 D043 D043 D043 D070 IPUR IIL D070 D060 D061A D063 with Schmitt Trigger buffer MCLR, T0CKI OSC1 (in EXTRC), EC(1) OSC1 (in HS) OSC1 (in XT and LP) GPIO/PORTB Weak Pull-up Current Input Leakage Current(2), (3) GPIO Weak Pull-up Current (GP3) I/O ports GP3/RB3/MCLR(4) OSC1 Output Low Voltage D080 D080A D083 D083A Output High Voltage D090 D090A D092 D092A OSC2 VOH I/O ports/CLKOUT(3) VDD - 0.7 VDD - 0.7 VDD - 0.7 VDD - 0.7 Capacitive Loading Specs on Output Pins D100 D101 Legend: Note 1: 2: 3: 4: COSC2 OSC2 pin CIO All I/O pins -- -- -- -- 15 50 pF pF In XT, HS and LP modes when external clock is used to drive OSC1. -- -- -- -- -- -- -- -- V V V V IOH = -3.0 mA, VDD = 4.5V, -40C to +85C IOH = -2.5 mA, VDD = 4.5V, -40C to +125C IOH = -1.3 mA, VDD = 4.5V, -40C to +85C IOH = -1.0 mA, VDD = 4.5V, -40C to +125C OSC2 VOL I/O ports/CLKOUT -- -- -- -- -- -- -- -- 0.6 0.6 0.6 0.6 V V V V IOL = 8.5 mA, VDD = 4.5V, -40C to +85C IOL = 7.0 mA, VDD = 4.5V, -40C to +125C IOL = 1.6 mA, VDD = 4.5V, -40C to +85C IOL = 1.2 mA, VDD = 4.5V, -40C to +125C TBD -- -- -- 225 -- -- -- TBD 1 5 5 A A A A VDD = 5V VPIN = 0V Vss VPIN VDD, Pin at high-impedance Vss VPIN VDD Vss VPIN VDD, XT, HS and LP oscillator configuration 0.85 VDD 0.85 VDD 0.85 VDD 0.7 VDD 1.6 TBD -- -- -- -- -- 250 VDD VDD VDD VDD VDD TBD V V V V V A VDD = 5V, VPIN = VSS For entire VDD range -- -- -- VDD VDD V V 4.5 VDD 5.5V Otherwise with TTL buffer VSS VSS VSS VSS VSS VSS VSS -- -- -- -- -- -- -- 0.8V 0.15 VDD 0.15 VDD 0.15 VDD 0.15 VDD 0.3 VDD 0.3 VDD V V V V V V V For 4.5 VDD 5.5V otherwise Min Typ Max Units Conditions DC CHARACTERISTICS Param No.
Sym VIL
TBD = To be determined. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC12F510/16F506 be driven with external clock in RC mode. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Negative current is defined as coming out of the pin. This specification applies when GP3/MCLR is configured as an input with pull-up disabled. The leakage current of the MCLR circuit is higher than the standard I/O logic.
DS41268B-page 88
Preliminary
(c) 2006 Microchip Technology Inc.
PIC12F510/16F506
TABLE 13-1:
Sym VOS VCM CMRR TRT VIVRF * Note 1:
COMPARATOR SPECIFICATIONS
Characteristics Min -- 0 +55* -- 0.550 Typ 3 -- -- 150 0.6 Max 10 VDD - 1.5 -- 400* 0.650 Units mV V dB ns V Internal Comments
Input Offset Voltage Input Common Mode Voltage Common Mode Rejection Ratio Response Time(1) Internal Voltage Reference
These parameters are characterized but not tested. Response time measured with one comparator input at (VDD - 1.5)/2, while the other input transitions from VSS to VDD - 1.5V.
TABLE 13-2:
Sym CVRES
COMPARATOR VOLTAGE REFERENCE (VREF) SPECIFICATIONS
Characteristics Min -- -- -- -- -- -- -- Typ VDD/24* VDD/32 -- -- 2K* -- Max -- -- 1/4* 1/2* -- 10* Units LSb LSb LSb LSb s Comments Low Range (VRR = 1) High Range (VRR = 0) Low Range (VRR = 1) High Range (VRR = 0)
Resolution Absolute Accuracy Unit Resistor Value (R) Settling Time(1)
* Note 1:
These parameters are characterized but not tested. Settling time measured while VRR = 1 and VR<3:0> transitions from 0000 to 1111.
TABLE 13-3:
Param No. A01 A03 A04 A05 A06 A07 A10 A25 A30 Sym NR EIL EDL EFS EOFF EGN -- VAIN ZAIN
A/D CONVERTER CHARACTERISTICS (PIC12F510/16F506)
Characteristic Resolution Integral Error Differential Error Full-scale Range Offset Error Gain Error Monotonicity Analog Input Voltage Recommended Impedance of Analog Voltage Source Min -- -- -- 2 -- -- -- VSS -- Typ -- -- -- -- -- -- guaranteed(2) -- -- Max 8 bits 1 -1 < EDL 1 5.5* 1 1 -- VDD 10 Units bit LSb LSb V LSb LSb -- V k VDD = 5.0V No missing codes to 8 bits VDD = 5.0V VDD VDD = 5.0V VDD = 5.0V VSS VAIN VDD Conditions
* These parameters are characterized but not tested. Data in the "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only are not tested. Note 1: Total Absolute Error includes integral, differential, offset and gain errors. 2: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes. 3: VREF current is from external VREF or VDD pin, whichever is selected as reference input. 4: When A/D is off, it will not consume any current other than leakage current. The power-down current specification includes any such leakage from the A/D module.
(c) 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 89
PIC12F510/16F506
TABLE 13-4:
Param No. A01 A03 A04 A05 A06 A07 A10 A25 A30 Sym NR EIL EDL EFS EOFF EGN -- VAIN ZAIN
A/D CONVERTER CHARACTERISTICS (PIC12F510)
Characteristic Resolution Integral Error Differential Error Full-scale Range Offset Error Gain Error Monotonicity Analog Input Voltage Recommended Impedance of Analog Voltage Source Min -- -- -- 2 -- -- -- VSS -- Typ -- -- -- -- -- -- guaranteed -- --
(2)
Max 8 bits 1 -1 < EDL 1 5.5* 1 1 -- VDD 10
Units bit LSb LSb V LSb LSb -- V k
Conditions
VDD = 5.0V No missing codes to 8 bits VDD = 5.0V VDD VDD = 5.0V VDD = 5.0V VSS VAIN VDD
* These parameters are characterized but not tested. Data in the "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only are not tested. Note 1: Total Absolute Error includes integral, differential, offset and gain errors. 2: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes. 3: VREF current is from external VREF or VDD pin, whichever is selected as reference input. 4: When A/D is off, it will not consume any current other than leakage current. The power-down current specification includes any such leakage from the A/D module.
DS41268B-page 90
Preliminary
(c) 2006 Microchip Technology Inc.
PIC12F510/16F506
13.4 Timing Parameter Symbology and Load Conditions
The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase (pp) and their meanings: pp 2 ck cy drt io S F H I L Fall High Invalid (High-impedance) Low P R V Z Period Rise Valid High-impedance To CLKOUT Cycle Time Device Reset Timer I/O port mc osc os t0 wdt MCLR Oscillator OSC1 T0CKI Watchdog Timer
T Time
Uppercase letters and their meanings:
FIGURE 13-5:
LOAD CONDITIONS
Legend: CL = 50 pF for all pins except OSC2 Cl VSS 15 pF for OSC2 in XT, HS or LP modes when external clock is used to drive OSC1
Pin
FIGURE 13-6:
EXTERNAL CLOCK TIMING
Q4 Q1 Q2 Q3 Q4 Q1
OSC1 1 2 3 3 4 4
(c) 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 91
PIC12F510/16F506
TABLE 13-5: EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +85C (industrial), -40C TA +125C (extended) Characteristic External CLKIN Frequency(2) Min DC DC DC Oscillator Frequency
(2)
AC CHARACTERISTICS Para No. 1A
Sym FOSC
Typ(1) -- -- -- -- -- -- -- -- -- -- -- -- -- -- 4/FOSC -- -- -- -- -- --
Max 4 20 200 4 4 20 200 -- -- -- -- 10,000 250 -- -- -- -- -- 25* 50* 15
Units
Conditions
MHz XT Oscillator mode MHz HS/EC Oscillator mode (PIC16F506 only) kHz LP Oscillator mode MHz EXTRC Oscillator mode MHz XT Oscillator mode MHz HS/EC Oscillator mode (PIC16F506 only) kHz ns ns s ns ns ns s ns ns s ns ns ns ns XT Oscillator LP Oscillator HS/EC Oscillator (PIC16F506 only) XT Oscillator LP Oscillator HS/EC Oscillator (PIC16F506 only) LP Oscillator mode XT Oscillator mode HS/EC Oscillator mode (PIC16F506 only) LP Oscillator mode EXTRC Oscillator mode XT Oscillator mode HS/EC Oscillator mode (PIC16F506 only) LP Oscillator mode
-- 0.1 4 --
1
TOSC
External CLKIN Period(2)
250 50 5
Oscillator Period
(2)
250 250 50 5
2 3
TCY TosL, TosH
Instruction Cycle Time Clock in (OSC1) Low or High Time
200 50* 2* 10
4
TosR, TosF
Clock in (OSC1) Rise or Fall Time
-- -- --
* Note 1: 2:
These parameters are characterized but not tested. Data in the Typical ("Typ") column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. When an external clock input is used, the "max" cycle time limit is "DC" (no clock) for all devices.
DS41268B-page 92
Preliminary
(c) 2006 Microchip Technology Inc.
PIC12F510/16F506
TABLE 13-6: CALIBRATED INTERNAL RC FREQUENCIES
Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +85C (industrial), -40C TA +125C (extended) Freq. Min Tolerance 1% 2% 5% 7.92 7.84 7.60 Typ(1) Max* Units 8.00 8.00 8.00 8.08 8.16 8.40 Conditions AC CHARACTERISTICS Param Sym No. F10
Characteristic
FOSC Internal Calibrated INTOSC Frequency(1)
MHz VDD = 3.5V TA = 25C MHz 2.5V VDD 5.5V 0C TA +85C MHz 2.0V VDD 5.5V -40C TA +85C (Ind.) -40C TA +125C (Ext.)
* Note 1:
These parameters are characterized but not tested. Data in the Typical ("Typ") column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
FIGURE 13-7:
I/O TIMING
Q4 Q1 Q2 Q3
OSC1
I/O Pin (input) 17 I/O Pin (output) Old Value 20, 21 19 18 New Value
Note:
All tests must be done with specified capacitive loads (see data sheet) 50 pF on I/O pins and CLKOUT.
(c) 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 93
PIC12F510/16F506
TABLE 13-7: TIMING REQUIREMENTS
Standard Operating Conditions (unless otherwise specified) AC CHARACTERISTICS Operating Temperature -40C TA +85C (industrial) -40C TA +125C (extended) Param No. 17 18 19 20 21 Sym TOSH2IOV TOSH2IOI TIOV2OSH TIOR TIOF Characteristic OSC1 (Q1 cycle) to Port out valid(2), (3) OSC1 (Q2 cycle) to Port input invalid (I/O in hold time)(2) Port input valid to OSC1 (I/O in setup time) Port output rise time
(2), (3)
Min -- TBD TBD -- --
Typ(1) -- -- -- 10 10
Max 100* -- -- 25** 25**
Units ns ns ns ns ns
Port output fall time(2), (3)
* These parameters are characterized but not tested. ** These parameters are design targets and are not tested. Note 1: Data in the Typical ("Typ") column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. 2: Measurements are taken in EXTRC mode. 3: See Figure 13-5 for loading conditions.
FIGURE 13-8:
RESET, WATCHDOG TIMER AND DEVICE RESET TIMER TIMING
VDD MCLR 30 Internal POR 32 DRT Timeout(2) Internal Reset Watchdog Timer Reset 31 34 I/O pin(1) 34
32
32
Note 1: 2:
I/O pins must be taken out of High-Impedance mode by enabling the output drivers in software. Runs in MCLR or WDT Reset only in XT, LP and HS modes.
DS41268B-page 94
Preliminary
(c) 2006 Microchip Technology Inc.
PIC12F510/16F506
TABLE 13-8: RESET, WATCHDOG TIMER AND DEVICE RESET TIMER
Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +85C (industrial) -40C TA +125C (extended) Characteristic Min 2000* 9* 9* 9* 9* 0.5* 0.5* -- Typ(1) -- 18* 18* 18* 18* 1.125* 1.125* -- Max -- 30* 40* 30* 40* 2* 2.5* 2000* Units ns ms ms ms ms ms ms ns Conditions VDD = 5.0V VDD = 5.0V (Commercial) VDD = 5.0V (Extended) VDD = 5.0V (Industrial) VDD = 5.0V (Extended) VDD = 5.0V (Industrial) VDD = 5.0V (Extended) AC CHARACTERISTICS Param Sym No. 30 31 32
TMCL MCLR Pulse Width (low) TWDT Watchdog Timer Time-out Period (No Prescaler) TDRT Device Reset Timer Period Standard Short
34
TIOZ
I/O high-impedance from MCLR low
* Note 1:
These parameters are characterized but not tested. Data in the Typical ("Typ") column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
FIGURE 13-9:
TIMER0 CLOCK TIMINGS
T0CKI 40 41
42
TABLE 13-9:
TIMER0 CLOCK REQUIREMENTS
Standard Operating Conditions (unless otherwise specified) Operating Temperature -40C TA +85C (industrial) -40C TA +125C (extended) Characteristic T0CKI High Pulse Width No Prescaler With Prescaler T0CKI Low Pulse Width No Prescaler With Prescaler T0CKI Period Min 0.5 TCY + 20* 10* 0.5 TCY + 20* 10* 20 or TCY + 40* N Typ(1) Max -- -- -- -- -- -- -- -- -- -- Units ns ns ns ns ns Whichever is greater. N = Prescale Value (1, 2, 4,..., 256) Conditions
AC CHARACTERISTICS Parm No. 40 41 42
Sym Tt0H Tt0L Tt0P
* Note 1:
These parameters are characterized but not tested. Data in the Typical ("Typ") column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
(c) 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 95
PIC12F510/16F506
14.0 DC AND AC CHARACTERISTICS GRAPHS AND CHARTS
Graphs and charts are not available at this time.
DS41268B-page 96
Preliminary
(c) 2006 Microchip Technology Inc.
PIC12F510/16F506
NOTES:
(c) 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 97
PIC12F510/16F506
15.0
15.1
PACKAGING
Package Marking Information
8-Lead PDIP Example
XXXXXXXX XXXXXNNN YYWW
12F510/P 017 0410
14-Lead PDIP XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN
Example PIC16F506-I/P 0410017
8-Lead SOIC (.150") XXXXXXXX XXXXYYWW NNN
Example PIC12F510-I /SN0410 017
Legend: XX...X Y YY WW NNN
e3
*
Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package.
Note:
In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.
* Standard PICmicro device marking consists of Microchip part number, year code, week code and traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.
DS41268B-page 98
Preliminary
(c) 2006 Microchip Technology Inc.
PIC12F510/16F506
15.2 Package Marking Information (Cont'd)
14-Lead SOIC (.150") XXXXXXXXXXX XXXXXXXXXXX YYWWNNN Example PIC16F506 -I/SL 0410017
8-Lead MSOP
Example
XXXXXX YWWNNN
602/MS 310017
14-Lead TSSOP
Example
XXXXXXXX YYWW NNN
16F506/ST 0410 017
(c) 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 99
PIC12F510/16F506
8-Lead Plastic Dual In-Line (P) - 300 mil (PDIP)
E1
D 2 n 1 E
A
A2
c
L A1
eB
B1 p B
MAX Number of Pins Pitch Top to Seating Plane A .140 .170 4.32 Molded Package Thickness A2 .115 .145 3.68 Base to Seating Plane A1 .015 Shoulder to Shoulder Width E .300 .313 .325 8.26 Molded Package Width E1 .240 .250 .260 6.60 Overall Length D .360 .373 .385 9.78 Tip to Seating Plane L .125 .130 .135 3.43 c Lead Thickness .008 .012 .015 0.38 Upper Lead Width B1 .045 .058 .070 1.78 Lower Lead Width B .014 .018 .022 0.56 Overall Row Spacing eB .310 .370 .430 10.92 Mold Draft Angle Top 5 10 15 15 Mold Draft Angle Bottom 5 10 15 15 * Controlling Parameter Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-018
Units Dimension Limits n p
MIN
INCHES* NOM 8 .100 .155 .130
MAX
MIN
MILLIMETERS NOM 8 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 9.14 9.46 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10
DS41268B-page 100
Preliminary
(c) 2006 Microchip Technology Inc.
PIC12F510/16F506
14-Lead Plastic Dual In-Line (P) - 300 mil (PDIP)
E1
D
2 n 1
E A A2
c eB A1 B1 B p
L
MAX Number of Pins Pitch Top to Seating Plane A .140 .170 4.32 Molded Package Thickness A2 .115 .145 3.68 Base to Seating Plane A1 .015 Shoulder to Shoulder Width E .300 .313 .325 8.26 Molded Package Width .240 .250 .260 6.60 E1 Overall Length D .740 .750 .760 19.30 Tip to Seating Plane L .125 .130 .135 3.43 c Lead Thickness .008 .012 .015 0.38 Upper Lead Width B1 .045 .058 .070 1.78 Lower Lead Width B .014 .018 .022 0.56 Overall Row Spacing eB .310 .370 .430 10.92 Mold Draft Angle Top 5 10 15 15 5 10 15 15 Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-005
Units Dimension Limits n p
MIN
INCHES* NOM 14 .100 .155 .130
MAX
MIN
MILLIMETERS NOM 14 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 18.80 19.05 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10
(c) 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 101
PIC12F510/16F506
8-Lead Plastic Small Outline (SN) - Narrow, 150 mil (SOIC)
E E1
p
D 2 B n 1
h 45
c A A2
L A1
MAX Number of Pins Pitch Overall Height A .053 .069 1.75 Molded Package Thickness A2 .052 .061 1.55 Standoff A1 .004 .010 0.25 Overall Width E .228 .244 6.20 Molded Package Width E1 .146 .157 3.99 Overall Length D .189 .197 5.00 Chamfer Distance h .010 .020 0.51 Foot Length L .019 .030 0.76 Foot Angle 0 8 8 c Lead Thickness .008 .010 0.25 Lead Width B .013 .020 0.51 Mold Draft Angle Top 0 15 15 Mold Draft Angle Bottom 0 15 15 * Controlling Parameter Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-057
Units Dimension Limits n p
MIN
INCHES* NOM 8 .050 .061 .056 .007 .237 .154 .193 .015 .025 4 .009 .017 12 12
MAX
MIN
MILLIMETERS NOM 8 1.27 1.35 1.55 1.32 1.42 0.10 0.18 5.79 6.02 3.71 3.91 4.80 4.90 0.25 0.38 0.48 0.62 0 4 0.20 0.23 0.33 0.42 0 12 0 12
DS41268B-page 102
Preliminary
(c) 2006 Microchip Technology Inc.
PIC12F510/16F506
14-Lead Plastic Small Outline (SL) - Narrow, 150 mil (SOIC)
E E1
p
D
2 B n 1 h 45 c A A2
L A1
MAX Number of Pins Pitch Overall Height A .053 .069 1.75 Molded Package Thickness .052 .061 1.55 A2 Standoff A1 .004 .010 0.25 Overall Width E .228 .244 6.20 Molded Package Width E1 .150 .157 3.99 Overall Length D .337 .347 8.81 Chamfer Distance h .010 .020 0.51 Foot Length L .016 .050 1.27 Foot Angle 0 8 8 c Lead Thickness .008 .010 0.25 Lead Width B .014 .020 0.51 Mold Draft Angle Top 0 15 15 Mold Draft Angle Bottom 0 15 15 * Controlling Parameter Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-065
Units Dimension Limits n p
MIN
INCHES* NOM 14 .050 .061 .056 .007 .236 .154 .342 .015 .033 4 .009 .017 12 12
MAX
MIN
MILLIMETERS NOM 14 1.27 1.35 1.55 1.32 1.42 0.10 0.18 5.79 5.99 3.81 3.90 8.56 8.69 0.25 0.38 0.41 0.84 0 4 0.20 0.23 0.36 0.42 0 12 0 12
(c) 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 103
PIC12F510/16F506
8-Lead Plastic Micro Small Outline Package (MS) (MSOP)
E E1
p D 2 n 1
B
c
A
A2
F Units Dimension Limits Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Foot Length Footprint (Reference) Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom n p A A2 A1 E E1 D L F c B .016 .030 .000 MIN
L
A1
INCHES NOM 8 MAX MIN
MILLIMETERS* NOM 8 0.65 BSC .043 .037 .006 0.75 0.00 4.90 BSC 3.00 BSC 3.00 BSC .031 8 .009 .016 15 15 0.40 0 0.08 0.22 5 5 0.60 0.95 REF 8 0.23 0.40 15 15 0.80 0.85 1.10 0.95 0.15 MAX
.026 BSC
.033 .193 BSC .118 BSC .118 BSC .024 .037 REF 0 .003 .009 5 5 .006 .012 -
* Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. BSC: Basic Dimension. Theoretically exact value shown without tolerances. See ASME Y14.5M REF: Reference Dimension, usually without tolerance, for information purposes only. See ASME Y14.5M JEDEC Equivalent: MO-187 Drawing No. C04-111
Revised 07-21-05
DS41268B-page 104
Preliminary
(c) 2006 Microchip Technology Inc.
PIC12F510/16F506
14-Lead Plastic Thin Shrink Small Outline (ST) - 4.4 mm (TSSOP)
E E1 p
D
2 n B 1
A c
L Units Dimension Limits MIN n p A A2 A1 E E1 D L c B .039 .033 .002 .246 .169 .193 .020 0 .004 .007 INCHES NOM 14 .026 BSC .041 .035 .004 .251 .173 .197 .024 4 .006 .010 12 REF 12 REF
A1 MILLIMETERS* MAX MIN NOM 14 0.65 BSC .043 .037 .006 .256 .177 .201 .028 8 .008 .012 1.00 0.85 0.05 6.25 4.30 4.90 0.50 0 0.09 0.19 1.05 0.90 0.10 6.38 4.40 5.00 0.60 4 0.15 0.25 12 REF 12 REF
A2
MAX
Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Molded Package Length Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom
1.10 0.95 0.15 6.50 4.50 5.10 0.70 8 0.20 0.30
* Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side. BSC: Basic Dimension. Theoretically exact value shown without tolerances. See ASME Y14.5M REF: Reference Dimension, usually without tolerance, for information purposes only. See ASME Y14.5M JEDEC Equivalent: MO-153 AB-1 Drawing No. C04-087
Revised: 08-17-05
(c) 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 105
PIC12F510/16F506
APPENDIX A:
Revision A
Original release.
REVISION HISTORY
Revision B
Page 3 - Special Microcontroller Features and LowPower Features sections. PIC12F510 Pin Diagram. Section 3.0 - Figure 3-1, Figure 3-2, Table 3-2, Table 3-3. Section 4.0 - First paragraph, Section 4.2 - Figure references, Tables 4-1 and 4-2 (Note 1). Section 5.0 - Table 5-2, Table 5-6 Title. Section 6.0 Section 7.0 - First paragraph, Section 7.7, Register 7-1, Register 7-2, Register 7-3, Figure 7-1, Figure 7-2, Sections 7.4 through 7.7, Table 7-1. Section 8.0 - Sections 8.0 through 8.2, Figure 8-1, Table 8-1. Section 9.0 - Table 9-2, Register 9-1, Register 9-2, Table 9-3. Section 10.0 - Registers 10-1 and 10-2 (Note 1), Table 10-2 (Note 2), Section 10.2.5, Section 10.3, Table 10-3, Table 10-4, Table 10-5, Section 10.4, Section 10.5, Section 10.6.1, Section 10.9, 10.9.1, 10.9.2, Section 10.11. Section 13.0 - 13.1 DC Characteristics, 13.2 DC Characteristics, Table 13-1, Table 13-3, Table 13-4.
DS41268B-page 106
Preliminary
(c) 2006 Microchip Technology Inc.
PIC12F510/16F506
INDEX
A
ALU ....................................................................................... 9 Assembler MPASM Assembler..................................................... 80 Microchip Internet Web Site.............................................. 108 MPLAB ASM30 Assembler, Linker, Librarian ..................... 80 MPLAB ICD 2 In-Circuit Debugger ..................................... 81 MPLAB ICE 2000 High-Performance Universal In-Circuit Emulator...................................................... 81 MPLAB ICE 4000 High-Performance Universal In-Circuit Emulator...................................................... 81 MPLAB Integrated Development Environment Software.... 79 MPLAB PM3 Device Programmer ...................................... 81 MPLINK Object Linker/MPLIB Object Librarian .................. 80
B
Block Diagram Comparator for the PIC12F510................................... 46 Comparator for the PIC16F506................................... 46 On-Chip Reset Circuit ................................................. 64 Timer0......................................................................... 39 TMR0/WDT Prescaler................................................. 42 Watchdog Timer.......................................................... 67 Brown-Out Protection Circuit .............................................. 68
O
OPTION Register................................................................ 20 OSC Selection .................................................................... 55 OSCCAL Register............................................................... 22 Oscillator Configurations..................................................... 58 Oscillator Types HS............................................................................... 58 LP ............................................................................... 58 RC .............................................................................. 58 XT ............................................................................... 58
C
C Compilers MPLAB C18 ................................................................ 80 MPLAB C30 ................................................................ 80 Carry ..................................................................................... 9 Clocking Scheme ................................................................ 14 Code Protection ............................................................ 55, 69 Configuration Bits................................................................ 55 Configuration Word (PIC12F510) ....................................... 56 Configuration Word (PIC16F506) ....................................... 57 Customer Change Notification Service ............................. 108 Customer Notification Service........................................... 108 Customer Support ............................................................. 108
P
PIC12F510/16F506 Device Varieties ................................... 7 PICSTART Plus Development Programmer....................... 82 POR Device Reset Timer (DRT) ................................... 55, 66 PD............................................................................... 68 Power-on Reset (POR)............................................... 55 TO............................................................................... 68 PORTB ............................................................................... 27 Power-down Mode.............................................................. 69 Prescaler ............................................................................ 41 Program Counter ................................................................ 23
D
DC ....................................................................................... 88 DC Characteristics (Extended) ........................................... 87 DC Characteristics (Industrial) ............................................ 86 DC Characteristics (Industrial, Extended) ........................... 88 Development Support ......................................................... 79 Digit Carry ............................................................................. 9
Q
Q cycles .............................................................................. 14
E
Errata .................................................................................... 3
R
RC Oscillator....................................................................... 59 Reader Response............................................................. 109 Read-Modify-Write.............................................................. 37 Register File Map PIC12F510 ................................................................. 16 PIC16F506 ................................................................. 16 Registers Special Function ......................................................... 17 Reset .................................................................................. 55 Reset on Brown-Out ........................................................... 68
F
Family of Devices PIC12F510/16F506....................................................... 5 FSR ..................................................................................... 24
I
I/O Interfacing ..................................................................... 27 I/O Ports .............................................................................. 27 I/O Programming Considerations........................................ 37 ID Locations .................................................................. 55, 69 INDF.................................................................................... 24 Indirect Data Addressing..................................................... 24 Instruction Cycle ................................................................. 14 Instruction Flow/Pipelining .................................................. 14 Instruction Set Summary..................................................... 72 Internet Address................................................................ 108
S
Sleep ............................................................................ 55, 69 Software Simulator (MPLAB SIM) ...................................... 80 Special Features of the CPU .............................................. 55 Special Function Registers ................................................. 17 Stack................................................................................... 23 STATUS Register ..................................................... 9, 18, 51
L
Loading of PC ..................................................................... 23
T
Timer0 Timer0 ........................................................................ 39 Timer0 (TMR0) Module .............................................. 39 TMR0 with External Clock .......................................... 41 Timing Diagrams and Specifications .................................. 91
M
Memory Organization.......................................................... 15 Data Memory .............................................................. 16 Program Memory (PIC12F510/16F506) ..................... 15
(c) 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 107
PIC12F510/16F506
Timing Parameter Symbology and Load Conditions........... 91 TRIS Registers.................................................................... 27
W
Wake-up from Sleep ........................................................... 69 Watchdog Timer (WDT) ................................................ 55, 66 Period.......................................................................... 66 Programming Considerations ..................................... 66 WWW Address.................................................................. 108 WWW, On-Line Support........................................................ 3
Z
Zero bit .................................................................................. 9
DS41268B-page 108
Preliminary
(c) 2006 Microchip Technology Inc.
PIC12F510/16F506
THE MICROCHIP WEB SITE
Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: * Product Support - Data sheets and errata, application notes and sample programs, design resources, user's guides and hardware support documents, latest software releases and archived software * General Technical Support - Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing * Business of Microchip - Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives
CUSTOMER SUPPORT
Users of Microchip products can receive assistance through several channels: * * * * * Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Development Systems Information Line
Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://support.microchip.com
CUSTOMER CHANGE NOTIFICATION SERVICE
Microchip's customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions.
(c) 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 109
PIC12F510/16F506
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: RE: Technical Publications Manager Reader Response Total Pages Sent ________
From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Y N Literature Number: DS41268B FAX: (______) _________ - _________
Device: PIC12F510/16F506 Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS41268B-page 110
Preliminary
(c) 2006 Microchip Technology Inc.
PIC12F510/16F506
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X Temperature Range /XX Package XXX Pattern Examples:
a) b) Device: PIC18F248/258(1), PIC18F448/458(1), PIC18F448/458T(2); PIC18F248/258T ,
(2)
c)
VDD range 4.2V to 5.5V PIC18LF248/258(1), PIC18LF448/458(1), PIC18LF248/258T(2), PIC18LF448/458T(2); VDD range 2.0V to 5.5V
PIC18LF258 - I/L 301 = Industrial temp., PLCC package, Extended VDD limits, QTP pattern #301. PIC18LF458 - I/PT = Industrial temp., TQFP package, Extended VDD limits. PIC18F258 - E/L = Extended temp., PLCC package, normal VDD limits.
Temperature Range:
I E
= -40C to +85C = -40C to +125C
(Industrial) (Extended)
Package:
PT L SO SP P
= = = = =
TQFP (Thin Quad Flatpack) PLCC SOIC Skinny Plastic DIP PDIP
Note 1: 2:
F = Standard Voltage Range LF = Wide Voltage Range T = in tape and reel PLCC, and TQFP packages only.
Pattern:
QTP, SQTP, Code or Special Requirements (blank otherwise)
(c) 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 111
WORLDWIDE SALES AND SERVICE
AMERICAS
Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Atlanta Alpharetta, GA Tel: 770-640-0034 Fax: 770-640-0307 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 San Jose Mountain View, CA Tel: 650-215-1444 Fax: 650-961-0286 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509
ASIA/PACIFIC
Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8676-6200 Fax: 86-28-8676-6599 China - Fuzhou Tel: 86-591-8750-3506 Fax: 86-591-8750-3521 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 China - Shunde Tel: 86-757-2839-5507 Fax: 86-757-2839-5571 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 China - Xian Tel: 86-29-8833-7250 Fax: 86-29-8833-7256
ASIA/PACIFIC
India - Bangalore Tel: 91-80-4182-8400 Fax: 91-80-4182-8422 India - New Delhi Tel: 91-11-5160-8631 Fax: 91-11-5160-8632 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Korea - Gumi Tel: 82-54-473-4301 Fax: 82-54-473-4302 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 Malaysia - Penang Tel: 60-4-646-8870 Fax: 60-4-646-5086 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-572-9526 Fax: 886-3-572-6459 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350
EUROPE
Austria - Wels Tel: 43-7242-2244-399 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820
02/16/06
DS41268B-page 112
(c) 2006 Microchip Technology Inc.

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